Total 10 system engineer job vacancies in Art / Design / Entertainment category in Singapore

About NSING:

As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products includes General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low Energy BLE and BMS (Battery Management System). When you join NSING, you will be part of a talented team in the Singapore R&D Center where we develop high performance MCU targeting for Industrial and Edge AI applications.

Your Role:

As a SoC Design Verification Engineer, you will be you would be part of a passionate team developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C co-simulation, to mixed-signal simulation and formal verification. You will be part of the Singapore team in developing high performance MCU chips.

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain test benches for complex digital designs using System Verilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Your Skills and Experiences:

• Education：Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 5 years+ prior industry experience of design verification including significant System Verilog and UVM usage.
• Technical skills:

-Deep knowledge of digital logic design, SOC architecture and microarchitecture

- Proficient in simulation-based verification methodologies and languages such as UVM and System Verilog

- Skilled in developing and maintaining test benches, test cases, and verification environments

- Experience across the full verification cycle from initial planning to final tape out

• Preferred skills:

- Knowledge of low-power design techniques and verification methodologies.

- Knowledge of hardware-software co-simulation mixed-signal verification techniques.

- Knowledge of gate level simulation methodologies.

Other Skills:

• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Flexibility and adaptability and demonstrates ability to manage multiple tasks and projects, prioritizing effectively to meet deadlines.

About NSING:

As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products includes General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low Energy BLE and BMS (Battery Management System). When you join NSING, you will be part of a talented team in the Singapore R&D Center where we develop high performance MCU targeting for Industrial and Edge AI applications.

Your Role:

As a SoC Design Verification Engineer, you will be you would be part of a passionate team developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C co-simulation, to mixed-signal simulation and formal verification. You will be part of the Singapore team in developing high performance MCU chips.

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain test benches for complex digital designs using System Verilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Your Skills and Experiences:

• Education：Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 5 years+ prior industry experience of design verification including significant System Verilog and UVM usage.
• Technical skills:

-Deep knowledge of digital logic design, SOC architecture and microarchitecture

- Proficient in simulation-based verification methodologies and languages such as UVM and System Verilog

- Skilled in developing and maintaining test benches, test cases, and verification environments

- Experience across the full verification cycle from initial planning to final tape out

• Preferred skills:

- Knowledge of low-power design techniques and verification methodologies.

- Knowledge of hardware-software co-simulation mixed-signal verification techniques.

- Knowledge of gate level simulation methodologies.

Other Skills:

• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Flexibility and adaptability and demonstrates ability to manage multiple tasks and projects, prioritizing effectively to meet deadlines.

Position Overview:

We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.

Responsibilities:

• Assist in the Physical Design process, supporting RTL to GDS implementation for semiconductor chips.
• Aid in achieving block-level timing closure by assisting with Design constraints optimization and timing analysis.
• Participate in formal checks to ensure designs meet functional and timing requirements.
• Assist with low-power checks and contribute to power consumption analysis for power efficiency optimization.
• Collaborate with the Design team to implement UPF (Unified power Format) for power management and control.
• Support block-level Place and Route (APR), Static timing analysis (STA), and other Physical Design tasks under supervision.
• Contribute to script development in Tcl, Perl, or Python for Design automation and flow enhancement.

Qualification/ Requirements:

• Bachelor’s degree in electrical engineering, Computer Engineering, or a related field.
• Minimum 1 year of experience in physical design for semiconductor chips.
• Basic understanding of RTL-to-GDS flow, timing closure, low-power design, and power analysis concepts.
• Familiarity with scripting languages such as Tcl, Perl, or Python is a plus.

Position Overview:

We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.

Responsibilities:

• Lead the physical design process, overseeing RTL to GDS implementation for semiconductor chips.
• Achieve block-level timing closure by optimizing design constraints, performing timing analysis, and applying optimization techniques.
• Conduct formal checks to ensure designs meet functional and timing requirements.
• Perform low-power checks and analyze power consumption to optimize power efficiency.
• Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
• Execute block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff processes.
• Utilize Synopsys and Cadence APR (Automated Routing and Place) tools for high-quality physical design.
• Develop and employ scripts in Tcl, Perl, or Python to automate design tasks and improve the design flow.
• Mentor junior engineers and provide technical guidance and support as needed.

Qualification/ Requirements:

• Bachelor's/master’s degree in electrical engineering, Computer Engineering, or a related field.
• 3-5 years of experience in physical design for semiconductor chips.
• Proficiency in RTL-to-GDS flow, timing closure, low-power design, and power analysis.
• Strong understanding of UPF for power management and control.
• Experience with block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff.
• Familiarity with Synopsys and Cadence APR/Sign-off tools.
• Proficiency in scripting languages such as Tcl, Perl, or Python for automation.
• Able to guide junior colleague when needed.
• Excellent problem-solving skills and ability to work effectively in a team environment.

The Design for Reliability (DfR) Engineer is responsible for applying engineering and statistical knowledge to prevent or reduce the likelihood of failure of internally developed products. The DfR Engineer uses various methodologies and tools to work closely with those who design, develop, test, manufacture, deliver and support our products and services to achieve operational reliability.

• Guide the project teams in the implementation of reliability engineering methodologies, techniques, standards, procedures and the application of appropriate statistical tools.
• With the project team, set reliability targets for products under development.
• Gather field reliability data, populate the reliability model and identify areas of concern.
• Calculate cumulative effect on final system reliability of individual part reliabilities, identify gaps and determine appropriate actions to achieve customer specified operational reliability.
• Conduct technical risk analysis such as a FMEA to determine specific risk areas. Develop tests to be conducted based as identified by FMEA results.
• Rationalize tests to be conducted to determine sample size, test methods and other details that will produce efficient, statistically valid results.
• Monitor the test program and recommend adjustments as needed to meet reliability targets.
• Participate in technical design reviews and contribute solutions to reliability related issues.
• Coordinate root cause analysis of failed items.
• Compile and communicate lessons learned and ensure prevention of failures by archiving captured knowledge for re-use.
• Monitor and analyze key reliability indicators during product development and after commercialization, and keep management informed.

Experience & Exposures:

• Technology or Manufacturing Center
• Maintainability
• Reliability Engineering

Key Competencies:

• Statisical Methods (Hypothesis Testing, ANOVA, Design of Experiments, etc)
• Reliability Calculations (Survivability, Mean-Time-To-Fail, etc)
• Mechanical System Design
• Testing

Previous Experience and Competencies:

• Bachelor in Mechanical Engineering or in related field.

Veronica Neo Shen Hwa - [email protected]

Personnel Reg No: R1110855

Manpower Staffing Services (S) Pte Ltd

EA Licence No: 02C3423

Position Overview: The Senior Design Engineer will lead the development of micro-architecture for ISP and CV related algorithms. They will utilize RTL design using Verilog/System Verilog coding and HLS tools like Catapult, and analyze metrics such as power, performance, and area to meet key objectives. They will also drive verification signoff in collaboration with architects and DV Engineers, and provide extensive support for FPGA tasks including emulation, validation, and debugging.

Responsibilities:

• Lead the development of micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Analyze and optimize metrics like power, performance, and area.
• Drive verification signoff with architects and DV Engineers.
• Lead FPGA tasks including emulation, validation, and debugging. Qualification/ Requirements:
• Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.

Qualification/ Requirements:

• Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
• Experience: Minimum 3 years of experience in ASIC design. Expertise in image signal processing projects is beneficial.
• Advanced proficiency in HDL languages (Verilog, System Verilog).
• In-depth knowledge of all phases of ASIC frontend design and sign-off.
• Extensive experience in image/vision/video data processing or algorithm acceleration.
• Proficiency in scripting languages like Python, Perl, or C/C++..
• Soft Skills: Excellent leadership, teamwork, and communication skills.
• Additional Notes: Strong analytical skills and the ability to lead complex projects independently and within teams.

Position Overview:

We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.

Responsibilities:

• Lead the physical design process, overseeing RTL to GDS implementation for semiconductor chips.
• Achieve block-level timing closure by optimizing design constraints, performing timing analysis, and applying optimization techniques.
• Conduct formal checks to ensure designs meet functional and timing requirements.
• Perform low-power checks and analyze power consumption to optimize power efficiency.
• Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
• Execute block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff processes.
• Utilize Synopsys and Cadence APR (Automated Routing and Place) tools for high-quality physical design.
• Develop and employ scripts in Tcl, Perl, or Python to automate design tasks and improve the design flow.
• Mentor junior engineers and provide technical guidance and support as needed.

Qualification/ Requirements:

• Bachelor's/master’s degree in electrical engineering, Computer Engineering, or a related field.
• 3-5 years of experience in physical design for semiconductor chips.
• Proficiency in RTL-to-GDS flow, timing closure, low-power design, and power analysis.
• Strong understanding of UPF for power management and control.
• Experience with block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff.
• Familiarity with Synopsys and Cadence APR/Sign-off tools.
• Proficiency in scripting languages such as Tcl, Perl, or Python for automation.
• Able to guide junior colleague when needed.
• Excellent problem-solving skills and ability to work effectively in a team environment.

Position Overview:

We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.

Responsibilities:

• Assist in the Physical Design process, supporting RTL to GDS implementation for semiconductor chips.
• Aid in achieving block-level timing closure by assisting with Design constraints optimization and timing analysis.
• Participate in formal checks to ensure designs meet functional and timing requirements.
• Assist with low-power checks and contribute to power consumption analysis for power efficiency optimization.
• Collaborate with the Design team to implement UPF (Unified power Format) for power management and control.
• Support block-level Place and Route (APR), Static timing analysis (STA), and other Physical Design tasks under supervision.
• Contribute to script development in Tcl, Perl, or Python for Design automation and flow enhancement.

Qualification/ Requirements:

• Bachelor’s degree in electrical engineering, Computer Engineering, or a related field.
• Minimum 1 year of experience in physical design for semiconductor chips.
• Basic understanding of RTL-to-GDS flow, timing closure, low-power design, and power analysis concepts.
• Familiarity with scripting languages such as Tcl, Perl, or Python is a plus.

Be part of a team in creating state-of-the-art Secure Low Power SoC ARM-based SoC/MCU for the Low-End , Mid and High-End performance MCU product line in a IC Design Environment.

Responsible:

• Engage design team and architects to strategies DFT Test plan for SoC top level
• Create DFT test modes, scan architecture, clocking and reset architecture.
• Plan Pin-Muxing and Pad and Boundary scan (BSDL) generation
• Execute JTAG TAP network generation and verification.
• Quality check with Spyglass analysis for scan using spyglass tool
• Execute Scan insertion using DC / Tessent tools
• Deploy Scan constraints development for Atspeed, shift and slow capture mode.
• Generate ATPG pattern generation using synopsys Tetramax tools
• Analyze and report on test coverage metrics to ensure comprehensive testing of designs.
• Implement improvements to enhance test coverage and efficiency.
• Verify No-timing and SDF simulation of ATPG patterns using VCS and NCSim tools
• Implement MBIST MBIST repair and verification using Mentor Graphic Tessent tools.
• Boundary scan verification
• Generate STIL test patterns for tester
• Silicon bring-up and failure debug

Requirements:

• Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
• Requires > 5 years or more of experience in DFT at IP and SoC top level. Proficient at using DC ,tetramax and MG tessent DFT tools
• Tape-out at least 5 chips and tested to pass on tester.
• Requires strong understanding of state of the DFT methodology , flat and hierarchical implement of DFT from IP to SoC top.
• Capable of understanding UPF to enable multiple power domain verification
• Capable of leading, review and guiding younger DFT engineers in their daily tasks
• Able to work in a team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills

Be part of a team in creating state-of-the-art Secure Low Power SoC ARM-based SoC/MCU for the Low-End , Mid and High-End performance MCU product line in a IC Design Environment.

Responsible:

• Engage design team and architects to strategies DFT Test plan for SoC top level
• Create DFT test modes, scan architecture, clocking and reset architecture.
• Plan Pin-Muxing and Pad and Boundary scan (BSDL) generation
• Execute JTAG TAP network generation and verification.
• Quality check with Spyglass analysis for scan using spyglass tool
• Execute Scan insertion using DC / Tessent tools
• Deploy Scan constraints development for Atspeed, shift and slow capture mode.
• Generate ATPG pattern generation using synopsys Tetramax tools
• Analyze and report on test coverage metrics to ensure comprehensive testing of designs.
• Implement improvements to enhance test coverage and efficiency.
• Verify No-timing and SDF simulation of ATPG patterns using VCS and NCSim tools
• Implement MBIST MBIST repair and verification using Mentor Graphic Tessent tools.
• Boundary scan verification
• Generate STIL test patterns for tester
• Silicon bring-up and failure debug

Requirements:

• Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
• Requires > 5 years or more of experience in DFT at IP and SoC top level. Proficient at using DC ,tetramax and MG tessent DFT tools
• Tape-out at least 5 chips and tested to pass on tester.
• Requires strong understanding of state of the DFT methodology , flat and hierarchical implement of DFT from IP to SoC top.
• Capable of understanding UPF to enable multiple power domain verification
• Capable of leading, review and guiding younger DFT engineers in their daily tasks
• Able to work in a team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills