Total 2,130 network engineer job vacancies in Art / Design / Entertainment category in Singapore

Company’s Profile
Julian Grey’s client is a solution provider for security and enterprise applications.

Responsibilities:

• Manage network, OS, storage, and backup tasks.
• Collaborate on system development, covering design, implementation, integration, and testing.
• Provide 24x7 support, implementing quick resolutions to minimize unplanned outages.
• Maintain detailed programmatic and technical documentation.
• Engage with external stakeholders and clients to ensure efficient resolution.

Requirements

• Degree in Computer Science, Computer Engineering, or Information Technology.

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Please WA Jian Wei @ 87389860
Shortlisted candidates will be notified

Quek Jian Wei
Reg No. R22110928
Julian Grey Corporate Advisory Pte. Ltd.

EA License No: 19C9568

• Perform design for manufacturability in all new projects.
• Provide PCB manufacturing technical advice to customers on their new projects.
• Perform feasibility studies and reviews for all new data received from customers.
• Adhoc duties as assigned.

Requirements:

• Degree/Diploma in Electrical & Electronics Engineering in Printed Wiring Board manufacturing environment
• Good communication, report writing and presentation skills
• Good analytical skill with ability to work independently
• Ability to communicate with all levels of staffs
• Entry level are welcome to apply as training will be provided.

Electronics MFG Industry

Loyang Area (Tpt pick up at designated area)

Interested applicants, please forward a detailed resume to [email protected]

Tempserv Pte Ltd
License No: 06C3745
Attention: Audris Teo / EA Personnel No: R1102063

Title: Senior Staff Design Verification Engineer(SoC)

Location: Singapore

About the role:

Our client is a global Precision Semiconductor Manufacturing business. They are market leaders in the development of ultra-low-power semiconductor solutions globally.

The company aims to pushin the boundaries of energy efficiency and enabling a new generation of intelligent, always-on devices. Their focus on innovation and sustainability has earned them recognition in the industry and made them a trusted partner for many leading manufacturers.

Deepening its commitment to Singapore as a strategic hub to drive breakthroughs in product and technical innovation, they are looking to hire a Senior Staff Design Verification Engineer(SoC),

a Subject Matter Expert who is the critical point of contact in terms of ensuring a smooth flow of end to end verification plans for complex ultra-low power technology designs, supporting all phases of strategic development, from creating test plans and testbench to performing gate-level-simulations and participation in FPGA and Pre-silicon bring-ups in Singapore and beyond.

Responsibilities:
Reporting to SoC Engineering Director, and this position will be focusing on the below:

• Develop and execute comprehensive verification plans for complex SoC designs, ensuring functional correctness across all levels (block, sub-system, and full-chip).
• Possess a deep understanding of various architectures and confidently integrate third-party IPs and VIPs.
• Demonstrate expertise in both digital and mixed-signal verification methodologies, with a focus on low-power design and verification challenges.
• Utilize SystemVerilog (UVM) and other industry-standard verification languages to create robust test benches and verification environments.
• Collaborate effectively with design engineers and architects to define verification strategies, identify potential issues, and achieve optimal coverage.
• Continuously improve verification methodologies and stay up-to-date on the latest verification trends and tools.

Qualifications:

• Bachelor's degree in Microelectronics or Electrical Engineering or a related field (Master's degree a plus).
• Minimum 5-8 years of experience in the field of semiconductor design verification.
• Proven track record of successfully verifying complex digital and mixed-signal SoC designs.
• Strong understanding of low-power design principles and verification techniques.
• Proficiency in Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Makefile
• Technologies: ARM SoC (Preferred), AMB, AXI/AHB/APB, DMA, Flow Control, Serial Devices, QoS, MIPI(CSI/DSI), Crypto,OTP, DSP, Low-Power

Interested? Here’s what to do next:

Please apply to the role with a recent copy of your CV. We will be in touch once we review your profile for suitability.

Singapore Employment Agency License No.: 16S8069

Privacy Statement: By submitting an application and sharing your personal information with us, you consent to such information being collected, held, used and disclosed in accordance with our Privacy Policy (https://www.wilsonhcg.com/privacy-policy)

Company Profile
Julian Grey's client is a precision engineering firm for laser, optics, and photonics.

Responsibilities

• Create comprehensive electrical circuit diagrams for automation and equipment systems.
• Assess, integrate, and validate hardware to ensure compliance with technical specifications.
• Produce CAD drawings depicting electrical circuits.
• Assist in diagnosing and resolving issues with system assembly, operation, and testing.
• Aid in equipment setup, problem-solving, and occasional installation.
• Provide assistance in testing new hardware and applications in-house.

Requirements

• Experience in automation machine design, proficiency in Electrical Design Software, electrical/electronic circuits and test instrumentation

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https://www.instagram.com/juliangreygroup/
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https://www.facebook.com/juliangreygroup/
Our telegram channel for job opportunities - https://t.me/jobopportunitiessg

Please WA Jian Wei @ 87389860

Only Shortlisted candidates will be notified

Quek Jian Wei

Reg No. R22110928

Julian Grey Corporate Advisory Pte. Ltd.

EA License No: 19C9568

Company's Profile
Julian Grey’s client is a global semiconductor equipment provider, specializing in inspection solutions for various industries. They have offices in APAC and are seeking motivated individuals to join their growing team.

Responsibilities

• Install and support semiconductor backend equipment locally and internationally.

Requirements

• Proficient in machinery automation with various systems and able to interpret machine and electrical diagrams, with familiarity in mechanical alignment, motor tuning, or vision systems as a plus.

Follow us for more updates, interview tips!
https://www.instagram.com/juliangreygroup/
https://www.linkedin.com/company/juliangreygroup/
https://www.facebook.com/juliangreygroup/
Our telegram channel for job opportunities - https://t.me/jobopportunitiessg

Interested Applicants
Please WA Jian Wei @ 87389860
Shortlisted candidates will be notified

Quek Jian Wei
Reg No. R22110928
Julian Grey Corporate Advisory Pte. Ltd.
EA License No: 19C9568

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

RESPONSIBILITIES

• To prepare intermediate engineering drawings, layout and equipment arrangement to support the Engineers in conducting their engineering planning, design and construction work. This includes consulting engineers on design and supporting them to and drafters in the development of engineering drawings.
• The main job challenge is to ensure design and drafting assignments are delivered to a high quality, using prevailing engineering design procedures, standards and codes.
• Maintaining Master Drawing Register.
• To ascertain that all inputs are delivered to engineering subcontractors in accordance with the MDR avoiding delay and rework.
• 3D Model Development - To maintain model accuracy.
• Perform Drafting Check - To maintain accuracy, quality, completeness & conformance for drafting and designing for the project standards.
• Project proposal document preparation - To provide technical support to project management/ proposal team.
• Design and drawing activities - To deliver the drawings by maintaining quality, complying with HSE standards and meeting the project deliverables schedule.
• Meetings Coordination - To resolve the engineering issues with help of drafting team and supervisors.
• Any other responsibilities, tasks assigned by the direct line Manager/ Management
• Any other tasks assigned by the Management.

Comply with HSE requirements:

• Environmental Aspects & Impacts Assessment.
• OHS Hazardous & Risk Assessment.
• Follow HSE Regulations.

Requirements

• Diploma in Electrical or equivalent.
• Qualification from Technical Institute.
• 10 years of working experience.
• Knowledge of standard drafting techniques and design procedures.
• Intermediate Microsoft Office.
• Advanced AutoCAD.
• Basic AVEVA E3D & Electrical.
• Advanced Autodesk Navisworks Simulate.
• Advanced Autodesk Navisworks Freedom.
• Advanced Adobe PDF.
• Strong communication and interpersonal skills.
• Ability to work independently with minimal supervision.
• Capable of delivering tasks efficiently and meeting deadlines.
• Strong team collaboration skills.

Job Responsibility:

· Prepare schematic design, site installation layout, calculations, technical reports and specifications etc for automation equipment panel.

· Liaise with external consultant teams, contractors and suppliers to resolve project electrical design issues.

· Generate BOM and RFQ document.

· Communicate with contractor for automation equipment panel fabrication.

· Prepare factory acceptance test document for automation equipment panel.

· Responsible for liaising with Project Manager on automation equipment panel acceptance before ship to site.

· Provide support on site installation.

· Updating of Circuit diagram, Control device and Equipment Installation layout.

Job Requirements:

· Degree/Diploma​/Higher Nitec​ in Electrical & Electronic Engineering

· Knowledge in automation design of the control system (Hardware & Software). Experience in motor control, hardware and software designs with controls using PLCs an advantage

· Fluency in English and Chinese, both written and oral to liaise with associates

· Good analytical reasoning, theoretical approach and communication skills

· Excellent interpersonal and Communication skills

· Self-motivated and able to work independently with minimum supervision

· Hands on experience on wiring assembly and installation will be an advantage.

· Proficient in MS office and other relevant software like AutoCAD or EPLAN 8 Electric.

· Fresh graduate can be considered.

Job Responsibilities:

• Circuit Design and Simulation:
  Design and optimize analog circuits using schematic capture and simulation tools to meet performance targets under various conditions.
• Digital Standard Cell Libraries:
  Develop high-performance, low-power digital standard cell libraries optimized for speed, power, and area.
• Innovative Cell Architectures:
  Propose and develop novel digital cell architectures to enhance efficiency and performance.
• Collaboration with Layout Teams:
  Work with layout designers to ensure accurate and efficient physical implementations while maintaining manufacturability standards.

Qualifications:

• Education:
  Bachelor’s degree in Electronics Engineering, Computer Science, or related field. Master’s or Ph.D. preferred.
• Experience:
  5+ years in high-performance, low-power analog design with tape-out and deep sub-micron process experience (12nm and below).
• Technical Skills:Proficient in analog circuit design, noise analysis, and power optimization.
  Skilled in tools like Cadence Virtuoso, Spectre, and HSPICE for schematic capture and simulation.
  Experienced in developing digital standard cell libraries for performance and efficiency.
  Strong understanding of deep sub-micron challenges and solutions.
• Communication:
  Excellent collaboration and presentation skills to work effectively with cross-functional teams and articulate complex concepts clearly.

Job Responsibilities:

• Strategize and Lead Low-Power Design Initiatives:
  Define and execute strategies for achieving low-power, high-performance physical design. Lead the development of innovative workflows and methodologies to minimize power consumption while ensuring design reliability and scalability.
• Oversee Full-Chip Floor Planning and Routing:
  Provide technical leadership in full-chip floor planning and place-and-route activities. Optimize chip area, performance, and power metrics, while mentoring junior engineers in advanced methodologies.
• Architect Power Distribution Networks:
  Design and validate robust power networks to meet demanding performance criteria. Conduct power integrity analysis to address IR drop, noise, and power grid optimization, ensuring alignment with low-power objectives.
• Drive Timing Closure and Integrity Signoff:
  Lead timing closure efforts across cross-functional teams. Address complex timing violations, optimize critical paths, and ensure successful power and signal integrity signoff for final design verification.
• Champion Physical Verification Processes:
  Oversee DRC and LVS verification, resolving escalated issues and ensuring designs comply with layout and manufacturing rules. Guide the team through pre-tape-out readiness.
• Facilitate Cross-Team Collaboration:
  Act as a key liaison among RTL, analog, and verification teams. Drive alignment between physical design and overall architecture while addressing challenges and providing technical guidance to stakeholders.
• Promote Continuous Improvement:
  Champion the adoption of emerging tools, techniques, and methodologies. Drive workflow innovations to enhance efficiency, scalability, and quality of low-power physical design.

Requirements:

• Educational Background:
  Bachelor’s degree in Electronics, Computer Science, Electrical Engineering, or a related field. Master’s or Ph.D. preferred.
• Experience:
  10+ years in physical design with expertise in high-performance, low-power semiconductor technologies (12nm and below). Proven tape-out success and leadership experience are essential.
• Advanced Technical Expertise:
  Deep expertise in full-chip floor planning, place-and-route, and physical verification (DRC and LVS). Advanced knowledge of power network architecture, IR drop, and noise analysis. Strong proficiency with timing closure processes and STA tools like PrimeTime.
• Software and Tools Proficiency:
  Extensive experience with industry-standard tools such as Synopsys IC Compiler, Cadence Innovus, and scripting languages like Perl, TCL, and Python.
• Place-and-Route Leadership:
  Expert-level experience in advanced place-and-route strategies for performance and power optimization.
• Leadership and Mentorship:
  Proven ability to lead teams, mentor junior engineers, and manage cross-disciplinary collaboration in a fast-paced environment.
• Preferred Expertise:
  Experience in deep sub-micron technologies (7nm, 5nm, etc.), multi-voltage designs, advanced low-power techniques, and design-for-manufacturing (DFM). Familiarity with emerging semiconductor trends is a strong advantage.

Job Responsibilities:

• Develop Low-Power Design Workflows:
  Own the design process to minimize power consumption while ensuring performance and reliability using advanced tools and techniques.
• Full-Chip Floor Planning and Routing:
  Lead floor planning and place-and-route efforts to optimize chip area and meet performance, area, and power goals.
• Power Network Design:
  Create and analyze robust power networks to ensure performance, minimize losses, and support low-power goals.
• Timing Closure and Signoff:
  Collaborate with teams to resolve timing issues and manage power and signal integrity for design verification.
• Physical Verification (DRC and LVS):
  Ensure compliance with layout and manufacturing rules through DRC and LVS for a tape-out-ready design.
• Cross-Team Collaboration:
  Work with engineers across functions to align designs with chip architecture and solve design challenges.
• Continuous Improvement:
  Stay updated on design advancements and improve workflows for better efficiency and low-power optimization.

Requirements:

• Educational Background:
  Bachelor’s degree or higher in Electronics, Computer Science, Electrical Engineering, or a related field. Advanced degrees (Master’s/Ph.D.) are a plus.
• Experience:
  Minimum X years in physical design with a focus on high-performance, low-power designs. Must have tape-out experience and familiarity with advanced semiconductor technologies (12nm and below).
• Technical Expertise:
  Proficient in full-chip floor planning, place-and-route, and physical verification (DRC and LVS). Strong knowledge of power network design, IR drop analysis, and timing closure with static timing analysis (STA) tools like PrimeTime.
• Software Knowledge:
  Experience with tools such as Synopsys IC Compiler, Cadence Innovus, and scripting languages like Perl, TCL, and Python.
• Place-and-Route Experience:
  Hands-on expertise in place-and-route methodologies for optimizing performance, power, and area.
• Soft Skills:
  Excellent communication and collaboration skills to work effectively in multidisciplinary teams. Strong problem-solving and critical thinking abilities to address design challenges.
• Preferred Skills:
  Experience with advanced low-power techniques, deep sub-micron technologies (7nm, 5nm, etc.), multi-voltage designs, and design-for-manufacturing (DFM) principles.

RESPONSIBILITY

• Assume a technical expertise in assessing sites, conducting detailed drawings, and estimating Solar project capacity and costs.
• Formulate comprehensive design specifications and functional requirements for the region, ensuring alignment with project needs.
• Complete system designs for projects including site plans, mechanical racking and attachment plans, single-line electrical drawings, specification of balance of system location and interconnection details.
• Conduct in-depth analysis of factors influencing system performance.
• Partner with the O&M Team to evaluate system performance, identify optimization opportunities, and drive continuous improvement initiatives.
• Perform software simulations of solar photovoltaic (PV) system performance & energy production
• Execute design calculations, encompassing voltage drop analysis, fault current assessments, and system optimization strategies.
• Ensure compliance with EPC contract specifications and regulatory requirements, mitigating risks and optimizing project outcomes including on-site engineering support.
• Collaborate closely with contractors to review and approve engineering drawing submissions, maintaining rigorous quality control standards.

QUALIFICATIONS & EXPERIENCE

• Degree/Diploma in Electrical Engineering discipline
• 3 to 5 years’ experience in Solar PV system design / engineering.

SKILLS/COMPETENCIES & PREFERRED CHARACTERISTICS

• Proactive self-starter with an ability to thrive in dynamic environments
• Solution-oriented approach with a track record of overcoming complex challenges and driving innovation
• Collaborative team player and able to guide the drafting team.
• Adaptability and willingness to embrace new technologies and methodologies
• Proficient in Microsoft Office and Excel capabilities for data analysis and reporting
• Proficient in design software such as PV AutoCAD,

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 3 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Candidates with no prior working experience are welcome to apply.

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-Level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D/Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design.
• Min. 5 years of experience in CMOS Analog IC design and simulation.
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent).
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D/Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 8 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Senior Design Engineer
5 days
9am-6pm
Kallang
Up to $7000

Responsibilities:

• Define requirements and features for semiconductor equipment
• Develop concepts and architecture of new equipment
• Design mechanical systems which involve the selection and use of motors, actuators, gear drives, pumps and valves.
• Produce detailed engineering drawings
• Perform design verification and validation testing to ensure compliance with specifications, safety regulations and product requirements.
• Improve design of legacy machines
• Application of analysis tools like Fish Bone Diagram, FMEA etc.

Requirements:

• Degree in Mechanical or Mechatronics Engineering
• More than 5 years of experience in semiconductor equipment design
• Good knowledge and experience in the following areas :
  1) Design of automation or semiconductor equipment
  2) High precision machine design
  3) Design of High Speed Pick and Place mechanisms
• Familiar with 3D CAD software
• Ability to plan, prioritize, and coordinate throughout the project cycle
• Equipment troubleshooting skills
• Ability to produce detailed Mechanical drawings and apply knowledge of Geometric Dimensioning & Tolerancing.

WhatsApp: +65 9837 8400

Lim Jun Yao Reg No.: R1989028

The Supreme HR Advisory Pte Ltd EA No.: 14C7279

Senior/Process Design Engineer (Wastewater Treatment)

Our client is a leading environmental solutions firm with strong expertise in EPCC, O&M and design & build. In line with their growth and expansion, they’re now looking for a Senior/Process Engineer to join their dynamic organization during an exciting time in their development.

Job Responsibilities

• Be responsible for designing, implementing, and optimizing wastewater treatment processes and systems
• Coordinate with cross-functional teams, including design, construction, and commissioning, to ensure seamless project execution.
• Prepare technical specifications for treatment plant
• Provide engineering support for tender activities, bids and proposals, and prepare testing and commissioning plans
• Manage contractors and suppliers, ensuring adherence to technical specifications and safety regulations
• Lead continuous improvement initiatives to enhance the reliability and effectiveness of wastewater systems.
• Ensure that treatment plants comply with regulatory standards and operate efficiently

Requirements

• Minimum Degree in Chemical Engineering, Environmental Engineering or related field
• Possess process/mechanical design experience with wastewater treatment projects
• Must be willing to be hands-on to be on site occasionally
• Must be able to draw and review drawings (i.e. create process flow diagrams (PFDs), piping and instrumentation drawings (P&IDs), perform detailed calculations related to plant process design)

Location: West

Interested candidates kindly forward your CV to [email protected] (Tan Yi Ling, Reg No: R21103172). You may email this great opportunity to someone who would be a great fit for this role.

All information will be kept strictly confidential. We regret to inform that only successful applicants will be contacted.

PeopleSearch Pte Ltd

EA License No: 16S8057

Job Description:

- Perform Civil, Structural Analysis and Design to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- To Lead and Mentor Junior Engineer in Performing Engineering Task

- Reporting to Principal Engineer / Management

Job Requirements:

- Candidate must possess at least a Master's Degree /Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 4 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

JOB DESCRIPTION

· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support; SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience with ASIC design flow

· Experience in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure and verification

· Good understanding of DFT

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

• Requires a BS in Electrical or Computer Engineering
• Some years of relevant experience is preferable
• Fresh graduates are encouraged to apply

Position Overview:

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

1. Experience in UVM verification methodology

2. Disciplined, quality-minded, and highly driven for excellence,

3. Excellent team player and good communication skills

4. MSEE/BSEE in Electrical Engineering or Computer Engineering, with 3 years of relevant experience, but are open to fresh graduates with outstanding results

5. Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities

6. Experience in video processing and video analytics is a plus

7. Passionate and strong in general programming is a plus

Company Profile
Julian Grey's client is a precision engineering firm for laser, optics, and photonics.

Responsibilities

• Create comprehensive electrical circuit diagrams for automation and equipment systems.
• Assess, integrate, and validate hardware to ensure compliance with technical specifications.
• Produce CAD drawings depicting electrical circuits.
• Assist in diagnosing and resolving issues with system assembly, operation, and testing.
• Aid in equipment setup, problem-solving, and occasional installation.
• Provide assistance in testing new hardware and applications in-house.

Requirements

• Experience in automation machine design, proficiency in Electrical Design Software, electrical/electronic circuits and test instrumentation

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Please WA Jian Wei @ 87389860

Only Shortlisted candidates will be notified

Quek Jian Wei

Reg No. R22110928

Julian Grey Corporate Advisory Pte. Ltd.

EA License No: 19C9568

Responsibilities

1. Develop design requirements of an NPU given system level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on in digital design experience is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.