Total 5 sales coordinator job vacancies in Engineering category in Singapore

Minimum qualifications:

• Bachelor’s degree in electrical engineering, or an engineering field.
• 10 years of experience as a Semiconductor IC, Quality, Reliability or Product Engineer.
• Experience in a technical team and/or people management.
• Experience with quality control, test coverage, and IC qualification.

Preferred qualifications:

• Over 10 years of experience in quality/reliability and semiconductor IC technology.
• Experience with semiconductor suppliers and manufacturing and supply chain processes.
• Experience in troubleshooting on different failure mode and root cause analysis.
• Experience with IC qualification, data review, and production release.
• Technical expertise of materials and processes for semiconductor ICs.

Background:

• Good understanding of materials, physical failure analysis and measurement techniques.
• Familiar with ISO 9001 or other quality management standards
• Able to work in a diverse team, use proactive approach, self-reliant & excellent decision-making skills.
• Capable of supplier, customer, and stakeholder management.

Responsibilities:

• Quality and reliability expert with a track record of improving the quality of semiconductor ICs during New Product Introduction (NPI) as well as the product life-cycle.
• Establish and be responsible for the quality and reliability throughout the product/IC life cycle.
• Work with cross-functional teams to define and ensure processes in place to provide the data required to manage quality and reliability.
• Interface with suppliers on a regular basis to track and drive root cause, resolve issues, track return material authorizations, corrective actions (OCAPs), and failure analysis.
• Work with suppliers and SMEs to provide material waivers including assessment, documentation, and protocols.
• Drive supplier process audits, product audits, 8D reports and summarize results for Exec Management as well as Global Operations team.
• Technical support of Global operations team for continuous improvement initiatives, as well as qualification and application of ICs.
• Travel up to 25%.

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 3 to 4 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 5 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.

Broadcom Central Engineering is looking for a qualified individual who can provide best-in-class development and support for Analog/Mixed Signal tool flows focused on advanced FINFET process nodes. This individual will be hands-on, heavily involved in day-to-day design/layout issues and in addition, interact with EDA vendors, the PDK development and process technology teams to provide timely solutions, and develop, maintain, and support utilities to improve productivity. If hired, the candidate is expected to be physically located in Broadcom's Singapore facility.

Responsibilities:

The candidate's main responsibilities include the following:

• Support (50%), enhance, and maintain PDKs and various Analog/Mixed-Signal design tools
• Develop software for automation in Skill, Perl, Unix Shell scripting
• Create documentation and provide hands-on training for design and layout engineers
• Work with EDA vendors to track and resolve issues
• Work with Technology Foundry teams (external/internal) to facilitate debugging and proper characterization of all tool related issues.

Requirements:

• Master in Electrical Engineering or Computer Science + 5 years of EDA experience.
• Expertise in the following CAD Tools: Virtuoso Studio 23.1, Cadence ADE-L/XL, Maestro, Spectre, Virtuoso Layout, Quantus QRC, Voltus-Fi APS/EMIR, EMX, and Synopsys Hspice, Primesim, StarRC, Quickcap, and Mentor Calibre/PERC
• Solid background in programming skills, circuit design, and device physics knowledge to help solve circuit design, layout, physical verification, and post-layout extraction challenges and problems. Looking for domain expertise/specialists in RCX, EM/IR , Substrate-Noise/Crosstalk and Aging/SHE circuit-simulation.
• Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation
• Expert in Cadence Skill, Perl, Unix Shell and utilities
• Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to detail, and the ability to work well in a team

• Accountable for the performance for a range of assigned production machines. To analyze systematically and uncover the root cause of any unscheduled failures and provide long term solutions to eliminate/reduce them.
• Able to perform independent hands-on troubleshooting and ability to direct team or single-handedly return machine back to day one condition in a timely manner.
• Train & guide Associate Engineers and Junior Engineers on the technical aspects of the machines. Specify and improve preventive and predictive measures to reduce unscheduled downtimes.

Preferences:

• Self driven and motivated to continuously learn and grow his/her machine related technical abilities. Able to work under pressure.
• In depth experiences in some of these areas: repair of semiconductor grade CVD (chemical vapour deposition) machines, RF heating. Knowledge in vacuum systems, fluid & thermodynamics, system controls, material science.
• To continually review and upgrade preventive/predictive maintenance to improve machine performance.
• Able to do programming in PLC or other platforms is advantageous

Qualifications

• Minimum Bachelor of Engineering in Electrical or Mechanical Engineering.
• Minimum 5 years working experience in machine design and equipment support.
• Job level will depend on the number of years of relevant working experience