Total 9 staff nurse job vacancies in Engineering category in D20 Bishan, Ang Mo Kio

Job Description:

• Design, development, testing and support of Printers firmware
• Making a software test plan and specification of a product
• Program Design, Coding and Debugging of a product
• Perform a software testing & reporting a software test result
• Assist with hardware troubleshooting & support hardware debugging
• Software requirement analysis and documentation
• Perform failure analysis
• Participate in Ad-hoc projects and assignments as required

Job Requirements:

• Candidate must possess at least Bachelor's Degree in Electronic/Computer Engineering/ Computer Science or Software Engineering or equivalent with 5 years of working experience
• Preferably have experience in development embedded system using C/C++ language
• Self-motivated and able to meet deadlines
• Willing to perform overtime
• Candidate with no working experience is welcome to apply too

Interested applicants, please send in your resume stating your date of availability, current and expected salary.

*Job Overview:*

We are seeking an experienced Facility Engineer to oversee and maintain our company’s infrastructure including clen room and ensure its efficient operation. The successful candidate will be responsible for the maintenance, troubleshooting, and repair of our facility's mechanical, electrical, plumbing, HVAC and security systems. You will play a crucial role in ensuring the safety, sustainability, and compliance of our physical assets.

*Key Responsibilities:*

- *Facility Maintenance:* Oversee the maintenance and operation of all building systems including HVAC, electrical, plumbing, fire safety, and security systems.

- *Repairs and Troubleshooting:* Diagnose and resolve technical issues with equipment and infrastructure to minimize downtime.

- *Preventive Maintenance:* Develop and implement preventive maintenance plans for critical systems to ensure the reliability and longevity of equipment.

- *Energy Management:* Optimize energy usage across the facility to improve efficiency and reduce costs.

- *Compliance:* Ensure the facility complies with relevant regulations, health and safety standards, and environmental requirements.

- *Project Management:* Lead facility improvement projects from design through implementation, including renovations, system upgrades, and installations.

- *Vendor Management:* Coordinate with third-party vendors and contractors for facility, security services and repairs.

- *Budgeting and Cost Control:* Manage facility budgets, monitor spending, and implement cost-saving measures.

- *Documentation:* Maintain detailed records of all maintenance activities, inspections, repairs, and compliance certifications.

*Qualifications:*

- *Education:* Bachelor’s degree (Diploma holder with Minium 7 years of experience) in Mechanical Engineering, Electrical Engineering, Facilities Management, or a related field.

- *Experience:* Minimum of 5+ years of experience as a Facility Engineer or in a similar role. Experience in managing Clean Room, commercial or industrial facilities is highly preferred.

- *Technical Skills:*

- Proficient in Computer Aided Design(CAD), Microsoft (excel,Words,PPT)

- Extensive knowledge of HVAC, electrical, plumbing, fire protection, and security systems.

- Strong troubleshooting skills in mechanical and electrical systems.

- *Other Skills:*

- Strong project management and organizational skills.

- Excellent communication and leadership abilities.

- Familiarity with local building codes and safety regulations.

*Working Conditions:*

- Ability to work in various environments, including outdoor, rooftop, and Clean Room.

- Occasional on-call work required for emergencies.

Company Overview

The team has more than 15 years of experience developing 1G/2.5G/5GBase-T Ethernet physical layer PHY and switch chips for data centers, enterprise networks, and gateways and has sucessfully developed multiple generations of the most competitive products.

The company is headquarted in Kunshan, and the R&D team is located in Kunshan, Suzhou, Shanghai, and Singapore and plans to setup an R&D center in Silicon Valley.

The company is currently developing Ethernet PHY, gateway, and TSN switching chips. The target market is automotive & unpiloted driving, China's intelligent manufacturing, rail transit, and intelligent grid building industry provide domestic chips with "Independent intellectual property rights, independent and controllable.

We offer attractive salary commensurate with work experience + AWS + Bonus + Stock options

Job Responsibilities:

1. Participate in the design and realization of high-speed low-power small-area network chips.
2. Responsible for the design and verification of analog and mixed-signal circuits, particularly the CMOS signal processing circuits with profession in one of these areas, RX(e.g., AFE, ADC), TX(Serializer, DAC), PLL, LDO, ESD/EMC suppression etc.
3. Support high-level functional development and verification of analog and mix-circuit circuitry.
4. Cooperate with product definition, layout implementation, lab test and verifications.

Job Requirements:

1. Master with minimum 2-3 years' experience or PhD with > 1 years' experience in high-performance analog/mixed-signal ICs.
2. Proven experience in IC design including chip tape-out and lab evaluation of design.
3. Solid experience in Using EDA CAD tools and performing Analog Custom Layout.
4. Experience in measuring IC performance and debug of design to correlate simulations to measurements.
5. Deep understanding of fundamental, including: detailed transistor level design, device physics, control/feedback loop stability analysis.
6. Direct project experience in at least one of the following areas a plus: ADC-DAC design PLL or clock/freq generation design.
7. Knowledge & experience in Verilog coding a plus.
8. Strong communication skills and good team player.

Company Overview

The team has more than 15 years of experience developing 1G/2.5G/5GBase-T Ethernet physical layer PHY and switch chips for data centers, enterprise networks, and gateways and has successfully developed multiple generations of the most competitive products.

The company is headquarted in Kunshan, and the R&D team is located in Kunshan, Suzhou, Shanghai, and Singapore and plans to setup an R&D center in Silicon Valley.

The company is currently developing Ethernet PHY, gateway, and TSN switching chips. The target market is automotive & unpiloted driving, China's intelligent manufacturing, rail transit, and intelligent grid building industry provide domestic chips with "Independent intellectual property rights, independent and controllable.

We offer attractive salary commensurate with work experience + AWS + Bonus + Stock options

Job Responsibilities:

1. Help define analog system design specifications and architectures.
2. Lead analog designs during product development.
3. Participate in the design and realization of high-speed low-power small-area network chips.
4. Responsible for the design and verification of analog and mixed-signal circuits, particularly the CMOS signal processing circuits with profession in one of these areas, RX(e.g., AFE, ADC), TX(Serializer, DAC), PLL, LDO, ESD/EMC suppression etc.
5. Support high-level functional development and verification of analog and mix-circuit circuitry.
6. Cooperate with product definition, layout implementation, lab test and verifications.

Job Requirements:

1. Master with > 7 years' experience or PhD with > 4 years' experience in high-performance analog/mixed-signal ICs.
2. Proven experience in IC design including chip tape-out and lab evaluation of design.
3. Solid experience in using EDA CAD tools and performing Analog Custom Layout.
4. Experience in measuring IC performance and debug of design to correlate simulations to measurements.
5. Deep understanding of fundamental, including: detailed transistor level design, device physics, control/feedback loop stability analysis.
6. Direct project experience in at least one of the following areas a plus: ADC-DAC design PLL or clock/freq generation design.
7. Knowledge & experience in Verilog coding a plus.
8. Strong communication skills and good team player.

Responsibilites:

• Responsible for Technical Support for the Operations and Enhancements/Change Requests.
• Support technical requirement of project implementation/rollout, enhancement, and maintenance of the system.
• Prepare Technical Documentations: Technical Specifications covering the design of input, program logic, output, including interfaces, and other required documentation.
• Perform Code Review, Unit Test, and support Integration Testing.
• Perform technical development and setup based on analysis of customized business/functional requirement using ABAP, ABAP for S/4 HANA (CDS, ADBC, AMDP), FIORI application, SAPUI5, SAP BTP Integration Suite: Modelling (flows, mapping, adapters), REST, OData, API.
• Responsible for managing and supporting databases for SAP system and complete SAP solutions.
• Participate in a global technical team, adapt quickly to dynamic environments, and develop elegant solutions to complex problems.
• Demonstrate problem solving and multi-tasking skills while working under pressure and exercising your knowledge of SAP Basis.

Requirement:

• Degree holder with at least 7 years working experience in SAP Basis, ABAP development, S/4 HANA, and SAP BTP in project implementation or support across SAP Modules SD, MM, FICO, PP, and QM.
• Good communication and interpersonal skill.
• ABAP Standard Report, ALV, Object Oriented, Dialog programming. SAPScript, Smartforms, Web Dynpro, Customer exit, Modification, BADI, BTE, Implicit and Explicit Enhancement.
• ABAP for S/4 HANA: Core Data Services (CDS), ABAP Database Connectivity (ADBC), ABAP Managed Database Procedures (AMDP), ABAP Test Cockpit, SQL Monitor and Performance.
• Experience in UI5 development.
• Interfaces: SAP PI (Mapping, IDoc, FTP, Web Service) and SAP BTP Integration Suite (Modelling (flows, mapping, adapters), REST, OData, API Management).
• Advanced troubleshooting and debug.
• Basic process knowledge in SAP functional modules: Logistic, and FICO.
• Proficiency in S/4 HANA User Access including Fiori application authorization, system performance tuning and troubleshooting.
• Experience with SAP S/4 HANA installation and BTP setup, system upgrades, and patches.
• Experience in high availability, disaster recovery, system refreshes and backup mechanisms.
• Ability to take ownership of work activities and take it to conclusion in a timely and efficient manner.
• Ability to communicate effectively, both written and verbal, with technical and non-technical multi-functional teams spread across regions.
• Proven problem-solving abilities and attention to detail.

Company Overview

The team has more than 15 years of experience developing 1G/2.5G/5GBase-T Ethernet physical layer PHY and switch chips for data centers, enterprise networks, and gateways and has sucessfully developed multiple generations of the most competitive products.

The company is headquarted in Kunshan, and the R&D team is located in Kunshan, Suzhou, Shanghai, and Singapore and plans to setup an R&D center in Silicon Valley.

The company is currently developing Ethernet PHY, gateway, and TSN switching chips. The target market is automotive & unpiloted driving, China's intelligent manufacturing, rail transit, and intelligent grid building industry provide domestic chips with "Independent intellectual property rights, independent and controllable.

We offer attractive salary commensurate with work experience + AWS + Bonus + Stock options

Job Responsibilities:

1. Participate in the design and realization of high-speed low-power small-area network chips.
2. Responsible for the design and verification of analog and mixed-signal circuits, particularly the CMOS signal processing circuits with profession in one of these areas, RX(e.g., AFE, ADC), TX(Serializer, DAC), PLL, LDO, ESD/EMC suppression etc.
3. Support high-level functional development and verification of analog and mix-circuit circuitry.
4. Cooperate with product definition, layout implementation, lab test and verifications.

Job Requirements:

1. Master with minimum 2-3 years' experience or PhD with > 1 years' experience in high-performance analog/mixed-signal ICs.
2. Proven experience in IC design including chip tape-out and lab evaluation of design.
3. Solid experience in Using EDA CAD tools and performing Analog Custom Layout.
4. Experience in measuring IC performance and debug of design to correlate simulations to measurements.
5. Deep understanding of fundamental, including: detailed transistor level design, device physics, control/feedback loop stability analysis.
6. Direct project experience in at least one of the following areas a plus: ADC-DAC design PLL or clock/freq generation design.
7. Knowledge & experience in Verilog coding a plus.
8. Strong communication skills and good team player.

Responsibilites:

• Responsible for Technical Support for the Operations and Enhancements/Change Requests.
• Support technical requirement of project implementation/rollout, enhancement, and maintenance of the system.
• Prepare Technical Documentations: Technical Specifications covering the design of input, program logic, output, including interfaces, and other required documentation.
• Perform Code Review, Unit Test, and support Integration Testing.
• Perform technical development and setup based on analysis of customized business/functional requirement using ABAP, ABAP for S/4 HANA (CDS, ADBC, AMDP), FIORI application, SAPUI5, SAP BTP Integration Suite: Modelling (flows, mapping, adapters), REST, OData, API.
• Responsible for managing and supporting databases for SAP system and complete SAP solutions.
• Participate in a global technical team, adapt quickly to dynamic environments, and develop elegant solutions to complex problems.
• Demonstrate problem solving and multi-tasking skills while working under pressure and exercising your knowledge of SAP Basis.

Requirement:

• Degree holder with at least 7 years working experience in SAP Basis, ABAP development, S/4 HANA, and SAP BTP in project implementation or support across SAP Modules SD, MM, FICO, PP, and QM.
• Good communication and interpersonal skill.
• ABAP Standard Report, ALV, Object Oriented, Dialog programming. SAPScript, Smartforms, Web Dynpro, Customer exit, Modification, BADI, BTE, Implicit and Explicit Enhancement.
• ABAP for S/4 HANA: Core Data Services (CDS), ABAP Database Connectivity (ADBC), ABAP Managed Database Procedures (AMDP), ABAP Test Cockpit, SQL Monitor and Performance.
• Experience in UI5 development.
• Interfaces: SAP PI (Mapping, IDoc, FTP, Web Service) and SAP BTP Integration Suite (Modelling (flows, mapping, adapters), REST, OData, API Management).
• Advanced troubleshooting and debug.
• Basic process knowledge in SAP functional modules: Logistic, and FICO.
• Proficiency in S/4 HANA User Access including Fiori application authorization, system performance tuning and troubleshooting.
• Experience with SAP S/4 HANA installation and BTP setup, system upgrades, and patches.
• Experience in high availability, disaster recovery, system refreshes and backup mechanisms.
• Ability to take ownership of work activities and take it to conclusion in a timely and efficient manner.
• Ability to communicate effectively, both written and verbal, with technical and non-technical multi-functional teams spread across regions.
• Proven problem-solving abilities and attention to detail.

Company Overview

The team has more than 15 years of experience developing 1G/2.5G/5GBase-T Ethernet physical layer PHY and switch chips for data centers, enterprise networks, and gateways and has successfully developed multiple generations of the most competitive products.

The company is headquarted in Kunshan, and the R&D team is located in Kunshan, Suzhou, Shanghai, and Singapore and plans to setup an R&D center in Silicon Valley.

The company is currently developing Ethernet PHY, gateway, and TSN switching chips. The target market is automotive & unpiloted driving, China's intelligent manufacturing, rail transit, and intelligent grid building industry provide domestic chips with "Independent intellectual property rights, independent and controllable.

We offer attractive salary commensurate with work experience + AWS + Bonus + Stock options

Job Responsibilities:

1. Help define analog system design specifications and architectures.
2. Lead analog designs during product development.
3. Participate in the design and realization of high-speed low-power small-area network chips.
4. Responsible for the design and verification of analog and mixed-signal circuits, particularly the CMOS signal processing circuits with profession in one of these areas, RX(e.g., AFE, ADC), TX(Serializer, DAC), PLL, LDO, ESD/EMC suppression etc.
5. Support high-level functional development and verification of analog and mix-circuit circuitry.
6. Cooperate with product definition, layout implementation, lab test and verifications.

Job Requirements:

1. Master with > 7 years' experience or PhD with > 4 years' experience in high-performance analog/mixed-signal ICs.
2. Proven experience in IC design including chip tape-out and lab evaluation of design.
3. Solid experience in using EDA CAD tools and performing Analog Custom Layout.
4. Experience in measuring IC performance and debug of design to correlate simulations to measurements.
5. Deep understanding of fundamental, including: detailed transistor level design, device physics, control/feedback loop stability analysis.
6. Direct project experience in at least one of the following areas a plus: ADC-DAC design PLL or clock/freq generation design.
7. Knowledge & experience in Verilog coding a plus.
8. Strong communication skills and good team player.

Job Description:

• Responsible for IP level and/or SOC level verification.
• Develop verification plan for complex digital IP from design spec, work closely with design engineers to identify important verification scenarios.
• Create verification environment/testbench with Bus Functional Model (BFM) using SystemVerilog, UVM and/or System C.
• Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs and to boost design quality prior to tape-out.
• Develop directed/use case/random test cases using SystemVerilog, analyse test results, debug tests and improve verification quality.
• Knowing to use Formal verification with SystemVerilog Assertion (SVA) to verify IP block is a plus.

Requirements:

• Bachelor/Master’s degree in Electrical & Electronics/Computer Engineering or equivalent.
• Familiar with AMBA bus protocol (AXI, CHI, ACE, APB).
• Experience with verification methodology such as SystemVerilog, OVM, UVM, SystemC.
• Experience with functional coverage/SVA assertions and test sequence/case writing.
• Experience with the full verification execution cycle.
• Experience in developing measurable verification plan.
• Experience with function verification for common SoC building blocks and verification IP for NOC/Interconnect/Fabric/PCIE, etc. are added advantages.
• Strong problem solver, communicator and team player.
• Scripting skills in Perl, Python, TCL, shell, etc.

This job can be supported by Career Conversion Programmes (CCP).