Total 2 software test engineer job vacancies in Others category in Singapore

What you will do

• Responsible for standard cell test key design of leading-edge process node (4nm/3nm/2nm), from schematic netlist to gds.
• Work with layout engineer for test key implementation and physical verification including DRC/LVS/ERC/ANT.
• Perform layout extraction, simulation, testing data collection and processing.
• Analyze simulation and silicon data including performance, power correlation, big data analysis, AI model training.
• Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
• Develop advanced library generation methodology and flow, including timing & power characterization, kit generation, regression, and quality assurance, involved with data analysis and machine learning as well.

What you bring

• BS/MS in Electrical and Electronic Engineering/Computer Engineering/Computer Science with minimum 8 years(MS) or 10 years(BS) industry experience.
• Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
• Experience of test chip design in FinFet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
• Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
• Strong communication and teamwork skills to collaborate effectively with cross-functional teams.

Location: One North, Singapore

Responsibilities:

• Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS.
• Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP.
• Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

Requirement:

At least 4 years of experience in Physical Design and Signoff

[Skills]

>> Synthesis:

PPA improvement through synthesis recipe exploration for better perf, power, and area.

>> Physical design :

Floor Planning, Place & Route followed by Timing and Physical Closure

>> Signoff :

PI : PG mesh spec selection, Bump/RDL planning, IR closure

PV : DRC, LVS, ANT, ERC closure

STA : Block level timing closure