Total 4 ux designer job vacancies in Sales / Marketing category in Singapore

We are seeking a highly skilled High-Speed IO Modeling designer to join our team. The ideal candidate will have a strong background in Electrical or Computer Engineering (Masters/PhD) , with a focus on high speed circuit modeling, statistical analysis, jitter analysis, digital signal processing, and signal integrity. The successful candidate will play a crucial role in developing IO performance models for chiplet-based high-speed communication protocols and generating complete high-speed link performance matrices based on advanced packaging.

Key Responsibilities:

• Develop IO performance models (Tx, Rx) for chiplet-based high-speed communication protocols such as UCIe, AIB, and others.
• Create complete high-speed link models by integrating IO performance models with advanced packaging interconnects.
• Generate comprehensive high-speed link performance matrices, considering various parameters such as technology node, area, latency, power, number of channels, micro bump pitch, and frequency of data rates.
• Collaborate with cross-functional teams to ensure the successful integration of IO performance models into the overall system design.
• Develop parameterised PDN model and fluent in analysing SI and PI simulations
• Stay up-to-date with the latest advancements in high-speed IO modelling techniques and technologies, and apply this knowledge to improve existing models and develop new ones.

Required Qualifications:

• Master's degree in Electrical or Computer Engineering with 2+ years of relevant experience, or a PhD in Electrical or Computer Engineering with 1+ years of relevant experience.
• Strong understanding of package/interconnect/I-O modelling, statistical analysis, jitter analysis, digital signal processing, and signal integrity.
• Experience in mixed-signal circuit design for High-Speed IOs (e.g AIB, AXI, UCIe).
• Proficiency in IBIS-AMI specification and model creation using Keysight ADS.
• Programming and scripting skills in one or more of the following: Python, Perl, C/C++, TCL, or AEL.

Preferred Qualifications:

• Ability to develop and implementing high-speed IO performance models using industry-standard tools/methodologies.
• Experience with advanced packaging technologies and their impact on high-speed link performance.
• Strong problem-solving skills and the ability to think creatively to overcome technical challenges.
• Excellent communication and collaboration skills, with the ability to work effectively in a team environment.

We are seeking a highly skilled High-Speed IO Modeling designer to join our team. The ideal candidate will have a strong background in Electrical or Computer Engineering (Masters/PhD) , with a focus on high speed circuit modeling, statistical analysis, jitter analysis, digital signal processing, and signal integrity. The successful candidate will play a crucial role in developing IO performance models for chiplet-based high-speed communication protocols and generating complete high-speed link performance matrices based on advanced packaging.

Key Responsibilities:

• Develop IO performance models (Tx, Rx) for chiplet-based high-speed communication protocols such as UCIe, AIB, and others.
• Create complete high-speed link models by integrating IO performance models with advanced packaging interconnects.
• Generate comprehensive high-speed link performance matrices, considering various parameters such as technology node, area, latency, power, number of channels, micro bump pitch, and frequency of data rates.
• Collaborate with cross-functional teams to ensure the successful integration of IO performance models into the overall system design.
• Develop parameterised PDN model and fluent in analysing SI and PI simulations
• Stay up-to-date with the latest advancements in high-speed IO modelling techniques and technologies, and apply this knowledge to improve existing models and develop new ones.

Required Qualifications:

• Master's degree in Electrical or Computer Engineering with 2+ years of relevant experience, or a PhD in Electrical or Computer Engineering with 1+ years of relevant experience.
• Strong understanding of package/interconnect/I-O modelling, statistical analysis, jitter analysis, digital signal processing, and signal integrity.
• Experience in mixed-signal circuit design for High-Speed IOs (e.g AIB, AXI, UCIe).
• Proficiency in IBIS-AMI specification and model creation using Keysight ADS.
• Programming and scripting skills in one or more of the following: Python, Perl, C/C++, TCL, or AEL.

Preferred Qualifications:

• Ability to develop and implementing high-speed IO performance models using industry-standard tools/methodologies.
• Experience with advanced packaging technologies and their impact on high-speed link performance.
• Strong problem-solving skills and the ability to think creatively to overcome technical challenges.
• Excellent communication and collaboration skills, with the ability to work effectively in a team environment.

We are seeking a highly skilled High-Speed IO Modeling designer to join our team. The ideal candidate will have a strong background in Electrical or Computer Engineering (Masters/PhD) , with a focus on high speed circuit modeling, statistical analysis, jitter analysis, digital signal processing, and signal integrity. The successful candidate will play a crucial role in developing IO performance models for chiplet-based high-speed communication protocols and generating complete high-speed link performance matrices based on advanced packaging.

Key Responsibilities:

• Develop IO performance models (Tx, Rx) for chiplet-based high-speed communication protocols such as UCIe, AIB, and others.
• Create complete high-speed link models by integrating IO performance models with advanced packaging interconnects.
• Generate comprehensive high-speed link performance matrices, considering various parameters such as technology node, area, latency, power, number of channels, micro bump pitch, and frequency of data rates.
• Collaborate with cross-functional teams to ensure the successful integration of IO performance models into the overall system design.
• Develop parameterised PDN model and fluent in analysing SI and PI simulations
• Stay up-to-date with the latest advancements in high-speed IO modelling techniques and technologies, and apply this knowledge to improve existing models and develop new ones.

Required Qualifications:

• Master's degree in Electrical or Computer Engineering with 2+ years of relevant experience, or a PhD in Electrical or Computer Engineering with 1+ years of relevant experience.
• Strong understanding of package/interconnect/I-O modelling, statistical analysis, jitter analysis, digital signal processing, and signal integrity.
• Experience in mixed-signal circuit design for High-Speed IOs (e.g AIB, AXI, UCIe).
• Proficiency in IBIS-AMI specification and model creation using Keysight ADS.
• Programming and scripting skills in one or more of the following: Python, Perl, C/C++, TCL, or AEL.

Preferred Qualifications:

• Ability to develop and implementing high-speed IO performance models using industry-standard tools/methodologies.
• Experience with advanced packaging technologies and their impact on high-speed link performance.
• Strong problem-solving skills and the ability to think creatively to overcome technical challenges.
• Excellent communication and collaboration skills, with the ability to work effectively in a team environment.

We are seeking a highly skilled High-Speed IO Modeling designer to join our team. The ideal candidate will have a strong background in Electrical or Computer Engineering (Masters/PhD) , with a focus on high speed circuit modeling, statistical analysis, jitter analysis, digital signal processing, and signal integrity. The successful candidate will play a crucial role in developing IO performance models for chiplet-based high-speed communication protocols and generating complete high-speed link performance matrices based on advanced packaging.

Key Responsibilities:

• Develop IO performance models (Tx, Rx) for chiplet-based high-speed communication protocols such as UCIe, AIB, and others.
• Create complete high-speed link models by integrating IO performance models with advanced packaging interconnects.
• Generate comprehensive high-speed link performance matrices, considering various parameters such as technology node, area, latency, power, number of channels, micro bump pitch, and frequency of data rates.
• Collaborate with cross-functional teams to ensure the successful integration of IO performance models into the overall system design.
• Develop parameterised PDN model and fluent in analysing SI and PI simulations
• Stay up-to-date with the latest advancements in high-speed IO modelling techniques and technologies, and apply this knowledge to improve existing models and develop new ones.

Required Qualifications:

• Master's degree in Electrical or Computer Engineering with 2+ years of relevant experience, or a PhD in Electrical or Computer Engineering with 1+ years of relevant experience.
• Strong understanding of package/interconnect/I-O modelling, statistical analysis, jitter analysis, digital signal processing, and signal integrity.
• Experience in mixed-signal circuit design for High-Speed IOs (e.g AIB, AXI, UCIe).
• Proficiency in IBIS-AMI specification and model creation using Keysight ADS.
• Programming and scripting skills in one or more of the following: Python, Perl, C/C++, TCL, or AEL.

Preferred Qualifications:

• Ability to develop and implementing high-speed IO performance models using industry-standard tools/methodologies.
• Experience with advanced packaging technologies and their impact on high-speed link performance.
• Strong problem-solving skills and the ability to think creatively to overcome technical challenges.
• Excellent communication and collaboration skills, with the ability to work effectively in a team environment.