Total 2 purchasing lead job vacancies in Science / R&D / Research category in Singapore

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.

Lead, Timing Signoff Engineer

(Senior Staff / Staff Engineer level)

Responsibilities:

· Reporting to the Technology, Advanced Development (located in Singapore), you will be the lead to plan timing related activities for the company’s next-generation technology development including

o defining signoff criteria, analysis, design methodology development

o day-to-day management of tape-outs driven by Advanced Development team.

o work closely with other members of the Advanced Development team and the broader engineering community to develop and deploy Timing signoff related flows and methodologies to support production chip development

· Define and own SoC timing signoff criteria, process corners, derates, uncertainties, and their tradeoffs. Be responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.

· Define and own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs. Drive clock tree planning and implementation for SoCs to achieve best energy, performance, and area.

· Be responsible for synthesis, PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions. Work with product development teams to rapidly deploy timing related methods in products.

· Plan and lead timing and other related activities for test chips owned by the Advanced Development team. As part of this effort, lead a small group of internal and/or contract resources.

· Maintain a relationship with and collaborate with 3rd party CAD tool vendors and fab during the development of new flows and methodologies. Validate and refine new techniques as part of a team that is building complex test chips in advanced FinFET nodes

Requirements

· Minimum Bachelor’s or Masters Degree with 10 years of hands-on experience in Static Timning Analysis, flows and methodologies for timing closure and have a strong understanding of noise, crosstalk, and OCV effects, aging, HTOL, soft errors in advanced FinFET nodes (16nm, 12nm, 7nm, 5nm)

· Proficient in Synthesis, place and route, UPF, Power integrity and reliability signoffs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection.

· Experience with large design STA and Timing Closure. Familiar with ECO techniques and implementation. Experience with STA signoff constraint authoring for full-chip level, tape-out signoff requirements, checklists, and associated automation.

· Experience in Cadence EDA tools (e.g., Genus, Innovus Tempus).

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.

Lead Standard Cell Characterization Engineer

(Senior Staff Engineer level)

Responsibilities:

· Reporting to the Technology, Advanced Development (located in Singapore), you will be the lead to execute library characterization flows, methodologies and optimize standard cell PPA. You will work closely with cross-functional teams to ensure the quality, reliability, and efficiency of the standard cell libraries.

· Lead, drive and execute Standard cell characterization, QA flows and its methodology development, deliver library view generation to enable digital, analog and mixed signal design and PnR flows

· Characterize and optimize standard cell libraries for FinFET technology, focusing on performance, power, and area metrics. Collaborate with circuit designers and layout engineers to define library requirements and ensure adherence to design rules and guidelines.

· Develop and execute test plans for standard cell library characterization, including timing, power, noise, and reliability analyses. Conduct transistor-level simulations and circuit-level measurements to validate and optimize standard cell performance.

· Perform detailed analysis of characterization data, identify deviations and anomalies, and propose corrective actions. Work closely with process engineers to understand and mitigate process variations that may impact standard cell library performance.

· Collaborate with the design automation team to enhance characterization methodologies and develop automation scripts for efficient library characterization. Participate in technology node evaluations and provide recommendations for standard cell library optimizations based on technology roadmaps.

Requirements

· Proven experience as a skilled and experienced Standard cell library Characterization Engineer with strong expertise in FinFET process technology.

· Masters or Bachelor’s Degree in Electronics Engineering with a minimum of 10 years of experience in standard cell design. This includes setting up library characterization flows and methodologies, QA flows, circuit design, layout, and simulation, with a strong emphasis on FinFET technologies (e.g., 16nm, 12nm, 6nm, or below).

· Proficient in defining, characterizing, and executing custom digital and analog cells, low power management cells, level shifters, retention flops, GPIOs, and memories.

· Expertise in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence Virtuoso Liberate/LV/Mx/Trio, Virtuoso, ADE, Genus, Innovus and Tempus.

· Solid understanding of FinFET technology and its impact on standard cell library design and characterization. Experience in characterizing standard cell libraries for advanced process nodes is highly desirable.

· Knowledge of standard cell architecture, design rules, and layout considerations. Familiarity with circuit and layout design, static timing analysis (STA), Physical design and power analysis methodologies.

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700