Total 7 digital art director job vacancies in Science / R&D / Research category in D12 Balestier, Serangoon, Toa Payoh

Working hrs: Mon to Fri (0800AM to 0100PM)

Location: Hougang

Requirements:

Science Laboratory, Art Assistant:

• GCE ‘O’ Level qualification.
• Minimum 3 years' experience in a primary school.
• Proficient in Microsoft Office (Word, Excel, PowerPoint).

Scope of works:

Science Laboratory cum Art Assistant

• Manage operational and maintenance tasks in Science Labs and Art Rooms.
• Operate simple life science equipment.
• Prepare and set up equipment for experiments.
• Prepare materials for art lessons.
• Maintain and update data records, including stocktaking.
• Perform general administrative tasks, such as filing and typing.

Job Description & Requirements

· Teach and conduct math classes and programs

· Develop and curate curriculum resources

· Oversee and train students in preparation for math competitions

· Facilitate an inclusive and collaborative classroom environment for math education

· Encourage students to express their creativity and problem-solving skills through mathematical projects

· Provide quality feedback on students' mathematical skills and development progress

· Participate in campus events, including parent meetings and festive occasions

· Perform any other duties and responsibilities as assigned by the Teaching Supervisor

Job Specification:

· Diploma / Bachelor’s Degree in Mathematics, Education or related fields

· Experience in teaching or tutoring, especially with children and young adults, is advantageous

· Patient, approachable, and passionate about teaching mathematics to kids and young adults

· Ability to connect, interact, and establish positive relationships with parents

· Demonstrates professionalism in appearance, dressing, and communication skills

· Energetic, with a positive can-do attitude

· Strong team player

· Fresh graduates are welcome to apply; training will be provided for candidates with a strong interest in education.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 5 years of ASIC design experience preferred.
• Familiar with ASIC design flow
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting
• A team player with good communication skills
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 8 years of ASIC design experience preferred.
• Familiar with ASIC design flow
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting
• A team player with good communication skills
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 3 years of ASIC design.
• experience preferred.
• Familiar with ASIC design flow.
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 3 years of ASIC design.
• experience preferred.
• Familiar with ASIC design flow.
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 5 years of ASIC design experience preferred.
• Familiar with ASIC design flow.
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving.