Total 10 staff nurse job vacancies in Science / R&D / Research category in Singapore

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.

Lead, Timing Signoff Engineer

(Senior Staff / Staff Engineer level)

Responsibilities:

· Reporting to the Technology, Advanced Development (located in Singapore), you will be the lead to plan timing related activities for the company’s next-generation technology development including

o defining signoff criteria, analysis, design methodology development

o day-to-day management of tape-outs driven by Advanced Development team.

o work closely with other members of the Advanced Development team and the broader engineering community to develop and deploy Timing signoff related flows and methodologies to support production chip development

· Define and own SoC timing signoff criteria, process corners, derates, uncertainties, and their tradeoffs. Be responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.

· Define and own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs. Drive clock tree planning and implementation for SoCs to achieve best energy, performance, and area.

· Be responsible for synthesis, PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions. Work with product development teams to rapidly deploy timing related methods in products.

· Plan and lead timing and other related activities for test chips owned by the Advanced Development team. As part of this effort, lead a small group of internal and/or contract resources.

· Maintain a relationship with and collaborate with 3rd party CAD tool vendors and fab during the development of new flows and methodologies. Validate and refine new techniques as part of a team that is building complex test chips in advanced FinFET nodes

Requirements

· Minimum Bachelor’s or Masters Degree with 10 years of hands-on experience in Static Timning Analysis, flows and methodologies for timing closure and have a strong understanding of noise, crosstalk, and OCV effects, aging, HTOL, soft errors in advanced FinFET nodes (16nm, 12nm, 7nm, 5nm)

· Proficient in Synthesis, place and route, UPF, Power integrity and reliability signoffs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection.

· Experience with large design STA and Timing Closure. Familiar with ECO techniques and implementation. Experience with STA signoff constraint authoring for full-chip level, tape-out signoff requirements, checklists, and associated automation.

· Experience in Cadence EDA tools (e.g., Genus, Innovus Tempus).

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.

Lead Standard Cell Characterization Engineer

(Senior Staff Engineer level)

Responsibilities:

· Reporting to the Technology, Advanced Development (located in Singapore), you will be the lead to execute library characterization flows, methodologies and optimize standard cell PPA. You will work closely with cross-functional teams to ensure the quality, reliability, and efficiency of the standard cell libraries.

· Lead, drive and execute Standard cell characterization, QA flows and its methodology development, deliver library view generation to enable digital, analog and mixed signal design and PnR flows

· Characterize and optimize standard cell libraries for FinFET technology, focusing on performance, power, and area metrics. Collaborate with circuit designers and layout engineers to define library requirements and ensure adherence to design rules and guidelines.

· Develop and execute test plans for standard cell library characterization, including timing, power, noise, and reliability analyses. Conduct transistor-level simulations and circuit-level measurements to validate and optimize standard cell performance.

· Perform detailed analysis of characterization data, identify deviations and anomalies, and propose corrective actions. Work closely with process engineers to understand and mitigate process variations that may impact standard cell library performance.

· Collaborate with the design automation team to enhance characterization methodologies and develop automation scripts for efficient library characterization. Participate in technology node evaluations and provide recommendations for standard cell library optimizations based on technology roadmaps.

Requirements

· Proven experience as a skilled and experienced Standard cell library Characterization Engineer with strong expertise in FinFET process technology.

· Masters or Bachelor’s Degree in Electronics Engineering with a minimum of 10 years of experience in standard cell design. This includes setting up library characterization flows and methodologies, QA flows, circuit design, layout, and simulation, with a strong emphasis on FinFET technologies (e.g., 16nm, 12nm, 6nm, or below).

· Proficient in defining, characterizing, and executing custom digital and analog cells, low power management cells, level shifters, retention flops, GPIOs, and memories.

· Expertise in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence Virtuoso Liberate/LV/Mx/Trio, Virtuoso, ADE, Genus, Innovus and Tempus.

· Solid understanding of FinFET technology and its impact on standard cell library design and characterization. Experience in characterizing standard cell libraries for advanced process nodes is highly desirable.

· Knowledge of standard cell architecture, design rules, and layout considerations. Familiarity with circuit and layout design, static timing analysis (STA), Physical design and power analysis methodologies.

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.

R&D – Senior Staff Engineer – Design Verification

Responsibilities:

· Craft test plans to construct robust testbench environments using System Verilog and the Universal Verification Methodology (UVM).

· Integrate third-party VIPs, automate the test environment for efficient boarding, and leverage your in-depth knowledge of SoC architectures, including AMBA AXI/AHB/APB protocols, DMAs, security mechanisms, clock management, and power-gating techniques.

· Develop cutting-edge drivers, monitors, predictors, and scoreboards using UVM, ensuring comprehensive verification coverage and functionality validation.

· Craft innovative tests to evaluate power and performance aspects, guaranteeing optimal efficiency and real-world reliability.

· Collaborate with cross-functional teams to perform gate-level simulations and support FPGA and post-silicon bring-up, ensuring a seamless transition from design to deployment.

· Continuously enhance productivity by developing support utilities for verification automation, testbench automation, and regression testing.

Requirements

· Bachelor's or Master's in Electrical Engineering, with 8-12 years of proven experience in block, sub-system, and full-chip verification.

· Disciplined, quality-minded, and highly driven for excellence.

· Expertise in understanding multiple architectures, integrating third-party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges.

· Strong proficiency in System Verilog simulation and C-based verification in an SoC environment.

· Extensive understanding and exposure to design verification for low-power, battery-operated designs.

· Familiarity with ARM processor-based designs and low-power design techniques (preferred).

· Mastery of System Verilog (UVM), Verilog, C/C++, Perl, Python, and Makefile.

· Experience with ARM SoC (preferred), AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, and QoS is required.

· Exposure to AI Edge inference, ISP, Video Codec, Video Processing, Audio Processing, MIPI (CSI/DSI), Crypto, OTP, DSP, and Low-Power technologies (preferred).

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

Staff Bumping R&D Engineer

Job Responsibilities:

• Support process and efficiency improvement activities
• Responsible to source new material for internal R&D activities
• Align with factories on product improvement and enhancement
• Initiate new product prototype with new innovative process, material and methodology
• Responsible for conducting & optimising advanced packaging processes (small scale, pre-research), e.g. Leadframe, Laminates, or Flipchip, Bumping, etc.;
• Contribute to developing advanced power module processes, output process files;
• Support product development team to transfer advanced packaging processes to HQ;
• Support process experts for advanced process technologies scouting, contribute to technical cooperation with universities and research institutes.
• Responsible for leading improvement, maintaining Process Flow, Control Plan as well and FMEA which the input may come from risk management, improvement activities, claims, audit findings, or internal process

Qualifications:

• Minimum of 2-5 years working experience in the same leadership capacity with similar semiconductor manufacturing
• Preferably with experience in bringing a product from R&D to low volume manufacturing
• Able to perform independently with minimal supervision and equipped with basic knowledge of the overall semiconductor assembly process as well as an understanding of automotive requirement
• A team player with strong analytical abilities, problem-solving skills in SPC, familiarity with 8 Discipline, Why-Why Analysis and Fault Tree Analysis and DOE will be an added advantage
• Knowledge and experience in Lean Manufacturing, Six Sigma and ISO/TS standards
• Candidate should possess at least a Degree or Master’s in Engineering (Mechanical, Electronics, Manufacturing, or Materials Engineering) or similar disciplines

Interested applicants, please kindly email your update resume to [email protected]. We regret to inform that only shortlisted candidates will be notified.

Staff Leadframe R&D Engineer

Job Responsibilities:

• Support process and efficiency improvement activities
• Responsible to source new material for internal R&D activities
• Align with factories on product improvement and enhancement
• Initiate new product prototype with new innovative process, material and methodology
• Responsible for conducting & optimising advanced packaging processes (small scale, pre-research), e.g. Leadframe, Laminates, or Flipchip, Bumping, etc.;
• Contribute to developing advanced power module processes, output process files;
• Support product development team to transfer advanced packaging processes to HQ;
• Support process experts for advanced process technologies scouting, contribute to technical cooperation with universities and research institutes.
• Responsible for leading improvement, maintaining Process Flow, Control Plan as well and FMEA which the input may come from risk management, improvement activities, claims, audit findings, or internal process

Qualifications:

• Minimum of 4-10 years working experience in the same leadership capacity with similar semiconductor manufacturing
• Preferably with experience in bringing a product from R&D to low volume manufacturing
• Able to perform independently with minimal supervision and equipped with basic knowledge of the overall semiconductor assembly process as well as an understanding of automotive requirement
• A team player with strong analytical abilities, problem-solving skills in SPC, familiarity with 8 Discipline, Why-Why Analysis and Fault Tree Analysis and DOE will be an added advantage
• Knowledge and experience in Lean Manufacturing, Six Sigma and ISO/TS standards
• Candidate should possess at least a Degree or Master’s in Engineering (Mechanical, Electronics, Manufacturing, or Materials Engineering) or similar disciplines

Interested applicants, please kindly email your update resume to [email protected]. We regret to inform that only shortlisted candidates will be notified.

Staff Power Module R&D Engineer

Support process and efficiency improvement activities

• Responsible to source new material for internal R&D activities
• Align with factories on product improvement and enhancement
• Initiate new product prototype with new innovative process, material and methodology
• Responsible for conducting & optimising advanced packaging processes (small scale, pre-research), e.g. Die Attach, Wire Bonding, Silver/Copper Sintering, Solder Reflow, Molding or Potting, etc.;
• Contribute to developing advanced power module processes, output process files;
• Support product development team to transfer advanced packaging processes to HQ;
• Support process experts for advanced process technologies scouting, contribute to technical cooperation with universities and research institutes.
• Responsible for leading improvement, maintaining Process Flow, Control Plan as well and FMEA which the input may come from risk management, improvement activities, claims, audit findings, or internal process

Qualifications:

• Minimum of 5 years working experience in the same leadership capacity with similar semiconductor manufacturing
• Preferably with experience in bringing a product from R&D to low volume manufacturing
• Able to perform independently with minimal supervision and equipped with basic knowledge of the overall semiconductor assembly process as well as an understanding of automotive requirement
• A team player with strong analytical abilities, problem-solving skills in SPC, familiarity with 8 Discipline, Why-Why Analysis and Fault Tree Analysis and DOE will be an added advantage
• Knowledge and experience in Lean Manufacturing, Six Sigma and ISO/TS standards
• Candidate should possess at least a Degree or Master’s in Engineering (Mechanical, Electronics, Manufacturing, or Materials Engineering) or similar disciplines

Interested applicants, please kindly email your update resume to [email protected]. We regret to inform that only shortlisted candidates will be notified.

Staff Lithography R&D Engineer

Job Responsibilities:

• Support process and efficiency improvement activities
• Responsible to source new material for internal R&D activities
• Align with factories on product improvement and enhancement
• Initiate new product prototype with new innovative process, material and methodology
• Responsible for conducting & optimising advanced packaging processes (small scale, pre-research), e.g. Lithography, etc.;
• Contribute to developing advanced power module processes, output process files;
• Support product development team to transfer advanced packaging processes to HQ;
• Support process experts for advanced process technologies scouting, contribute to technical cooperation with universities and research institutes.
• Responsible for leading improvement, maintaining Process Flow, Control Plan as well and FMEA which the input may come from risk management, improvement activities, claims, audit findings, or internal process

Qualifications:

• Minimum of 5 years working experience in the same leadership capacity with similar semiconductor manufacturing
• Preferably with experience in bringing a product from R&D to low volume manufacturing
• Able to perform independently with minimal supervision and equipped with basic knowledge of the overall semiconductor assembly process as well as an understanding of automotive requirement
• A team player with strong analytical abilities, problem-solving skills in SPC, familiarity with 8 Discipline, Why-Why Analysis and Fault Tree Analysis and DOE will be an added advantage
• Knowledge and experience in Lean Manufacturing, Six Sigma and ISO/TS standards
• Candidate should possess at least a Degree or Master’s in Engineering (Mechanical, Electronics, Manufacturing, or Materials Engineering) or similar disciplines

Interested applicants, please kindly email your update resume to [email protected]. We regret to inform that only shortlisted candidates will be notified.

Responsibilities:

• Providing and building new test boards and low noise analog systems.
• Analyzing and improving the electrical system and setting up and conducting test plans to validate the system's design standards.
• Engaging with scientists in the US to understand the issues associated with PCB circuit utilized in low-noise, high-speed imaging sensor.
• Facilitates flawless integration tests at the subsystem and system levels by working with researchers, sensor designers, and characterization specialists.
• Managing suppliers to ensure that design specifications are stated and met.

Requirements:

• Degree/Masters/Doctoral Academic Program in Electrical Engineering
• 4 years’ experience in a related industry.
• Known expertise in the design of electrical circuits and hardware such as power integrity, low noise mixed signal circuit design, signal integrity, PCB layout, debugging, and validation.

Interested candidates who wish to apply for the advertised position, please click on the APPLY button below to send in your resume or send to [email protected]

EA License No: 13C6305

Reg. No.: R1985234

For candidate who applied for the advertised position is deemed to have consented to us that we may collect, use or disclose your personal information for purpose in connection with the services provided by us

Responsibilities:

As part of our small and dynamic team you play a key role in the design and development of our Inspection and Metrology machines. In your role you will work hands-on on the mechanical integration, process optimization and automation of the machine. Your work will involve integration of the mechatronic, optical and SW building blocks and will hence work closely together with Mechanical design, Hardware, Optics and SW teams.

It is your job to analyse customer requirements, build up a deep understanding of the problem and translate these in automated solutions that you detail clearly in measurable design requirements. To verify the solutions, you will build and test high-speed mechatronic setups for spec validation and critical parameter analysis. Once these are confirmed, you will coordinate the design and implementation in the different teams to eventually integrate tested modules and building blocks in the machine and assess the impact of the integration on the overall machine performance.

You get the chance to confirm high speed Pick and Place handling capabilities at key customers on site and broaden your customer and application know how along the way.

Furthermore you seek the challenge of understanding, analyzing, (re-)defining, and implementing sophisticated material handling flows until the level of detailed micro-sequences.

You will often write PLC level test sequences for mockup validation and data collection. Once the system is validated, translate these sequences into SW requirements.

You consider the total system life cycle, the birth to death concept extends to maintenance, replacement and decommission.

Requirements:

• MS degree or BS degree with outstanding skill in electro-mechanical, electronics, software or mechanical engineering.
• 7+ years relevant experience in an automation oriented engineering role in a high-end equipment company, covering most of following technical domains: machine conceptual and mechanical design, setting up specifications, PLC controller hardware and software design, user interface, SW (describing, testing of flows), conversion, test protocols, debugging, characterization, lead improvement projects
• Strong analytical capabilities
• Programming skills are a plus (PLC controllers, C, C++ Python, VBA, …)
• Independent thinking, challenging existing ideas and approaches
• Hands-on, self-organized, taking initiative and ownership
• Occasional travel within Asia & Europe
• Proficient in English

Our client is a emergent brand name in the medical technology (Medical Electronics – Medical Devices) sector. We are looking for like-minded individuals who are passionate to join them to develop their next generation of medical electronics.

R&D Staff / Senior Hardware Engineer (Tuas West)

Company is less than 5 minutes by walking from MRT station

Responsibilities

• You will be part of a team of R&D engineers in Singapore including engineers from the Mechanical, Software, Electronics and Systems Engineering discipline.
• Your role in EE design starts from requirements capture, designing or supporting the design of hardware architecture, component selection and evaluation, schematics design as well as confirming the layout design and PCB bring up.
• From there; you will also be handling system implementation as well as testing; including supporting any EMI/EMC pre-compliance.
• Last but not least, you will be handling the technical documentation and supporting production team for device rollout.

Requirements

• Bachelor degree or above in Electrical / Electronics Engineering or Electronics & Communications Engineering with at least 8-12 years of experience in hardware design.
• Proven experience in designing Hi-speed mixed signal Board. Should be capable of handling 6–10-layer boards design with layout vendor.
• Knowledge of Thermal analysis and signal integrity is a good to have.
• Power supply design using DC-DC converters and linear regulators. Knowledge of high power electronics is optional.
• Communication Interface design: RS232/UART, SPI, I2C, USB
• Experience in working with Wireless modules like Bluetooth and Wi-Fi.
• Knowledge of TFT Display interfaces and camera interfaces (optional).
• Sound Knowledge of different motors (DC, BLDC and Stepper) and their drivers.
• Sound Knowledge of ADCs and DACs.
• Knowledge of optical (opto-interrupters, LED driver, photo detector) circuits and audio interfaces (Speaker, Buzzer etc.)
• Sound Knowledge of different EMI/EMC Tests and capability of fixing the issues.
• Battery power management including charging circuit design and fuel gauge.
• Hands On experience of with PCB design ECAD tools like Mentor graphics/Orcad/Altium etc.
• Hands on experience with Simulation tools like LT spice or equivalent.
• Hands on experience with lab tools DSOs, Multimeter, Signal generators etc.

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700