Total 5 quality control engineer job vacancies in Singapore

Description

Company Overview

Ambiq's mission is to?develop the lowest-power semiconductor solutions?to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world.?Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 250 million units by 2024. For more information, visit?www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

Scope

As the Staff Embedded Software Engineer at Ambiq, you will drive the development and testing of AmbiqSuite SDK on Ambiq SoC devices and emulation platforms.

This role will work within our global MCU software development team and will work closely with architecture team and local MCU SoC design team, focusing on MCU software development and test activities.

A successful candidate should be a fast-learning, result-driven, and self-motivated team player with an “always learning” mindset. He should have an inquiring spirit and be comfortable in a lab environment and in executing hands-on debugging for embedded systems.

The person in this role will be responsible for extending the hardware adaptation layer (HAL) and device drivers of the SDK to new platforms as well as enhancing its features and content. The candidate will be involved in the extension of the SDK to cover new MCU members of the family as they become available.

Responsibilities

• Work with our software architects to define the hardware abstraction layer (HAL) and board support package (BSP) of the SDK.
• Design, develop and maintain HAL interfaces for MCU common blocks, such as Cache, MPU, TCM, MRAM/Flash, clock, power and MCU control etc.
• Design, develop and maintain examples and software testcases for MCU common blocks.
• Take a key role in the pre-silicon verification on FPGA, as well as post-silicon bring up, verification, and debug focusing on MCU core and common blocks.
• Design, develop and maintain real-time OS ports for Ambiq MCUs.
• Support design verification (DV) and validation engineers, field engineers, and key customers as needed.

Requirements

• MS in ECE or Computer Science and 6+ years of experience or BS ECE/CS with 8+ years of experience;
• Deep understanding of ARM architectures, M-profile preferred;
• Deep understanding of embedded RTOS required, Zephyr and FreeRTOS preferred;
• Experience with developing embedded MCU code in C and assembly language on Arm Cortex-M Processors;
• Experience with at least one MCU IDE from ARM, Keil, IAR, Eclipse, O-zone or other;
• Familiarity with MCU peripherals such as SPI, I2C, UART etc.;
• Good hands-on experience on lab equipment such as oscilloscopes, logic analyzers etc. for debugging issues;
• Experience with Jira, Confluence and collaboration tools;
• Experience with source code control systems (git) required;
• Understanding of software testing and test automation principles;
• Excellent problem-solving skills dealing with complex system level issues related to HW/SW debug;
• Experience with scripting languages required and python experience is specifically desirable;
• Strong communication and documentation skills.

What you need

We're seeking passionate technologists who thrive on breaking boundaries, solving complex challenges, and driving transformative solutions.

At Ambiq, you'll collaborate with a dynamic team that values relentless innovation, customer-centric thinking, and continuous learning. If you're a self-motivated, creative problem-solver eager to push technological limits and make a meaningful impact in energy efficiency, this is your opportunity to grow, excel, and turn groundbreaking ideas into reality.

Most importantly, the successful candidate will be able to live the Ambiq Shared Values:

• Innovate: We tenaciously find ways to break down the barriers to possible solutions
• Collaborate: We proactively communicate and encourage each other to be better.
• Focus: We keep the voice of the customer at the center of everything we do.
• Learn: We strive for continuous improvement and are always curious.
• Achieve: We execute on quality and follow through on our commitments.

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 250 million units by 2024. For more information, visit www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

We are seeking a talented RTL Engineer to join our team in Singapore. As an RTL Engineer, you'll ensure the highest quality products by developing and implementing robust methodologies. Work alongside a talented team of engineers to deliver innovative solutions that meet the evolving needs of our customers.

Responsibilities

• Own and be responsible for pre-tape out quality for digital SOC modules on the MCU
• Explore architecture and develop micro-architecture.
• RTL development for IPs and SOCs using Verilog
• 3rd party IP identification, selection, and integration
• Collaboration with verification and FPGA teams in test plan development and debug
• Collaborate with the Physical Design team to close the design on timing and power targets
• Assist in silicon bring-up and validation;
• Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues

Requirements

• Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 5-8 years of experience.
• Possess deep and broad knowledge of current and emerging SOC design technologies.
• Have expert knowledge in designing, implementing, and troubleshooting IPs and SOC
• Demonstrate a deep understanding of customer needs and the competitive landscape.
• Ability to estimate the impact of and help plan and lead the implementations and have a positive impact on the entire output
• Can architect and guide programs across the full range of technical areas.

What You'll Need:

The successful candidate must be self-motivated, creative, and comfortable learning exciting new technologies. This is an opportunity for growth and work on complex, engaging, and challenging projects.

Most importantly, the successful candidate will be able to live the Ambiq Shared Values:

• Innovate: We tenaciously find ways to break down the barriers to possible solutions
• Collaborate: We proactively communicate and encourage each other to be better.
• Focus: We keep the voice of the customer at the center of everything we do.
• Learn: We strive for continuous improvement and are always curious.
• Achieve: We execute on quality and follow through on our commitment

Scope

We are looking for a skilled and experienced Standard cell library Characterization Engineer with strong expertise in FinFET process technology. Your primary responsibility will be to lead and execute library characterization flows, methodologies and optimize standard cell PPA. You will work closely with cross-functional teams to ensure the quality, reliability, and efficiency of the standard cell libraries.

Specific Responsibilities

• Lead, drive and execute Standard cell characterization, QA flows and its methodology development, deliver library view generation to enable digital, analog and mixed signal design and PnR flows
• Characterize and optimize standard cell libraries for FinFET technology, focusing on performance, power, and area metrics. Collaborate with circuit designers and layout engineers to define library requirements and ensure adherence to design rules and guidelines.
• Develop and execute test plans for standard cell library characterization, including timing, power, noise, and reliability analyses. Conduct transistor-level simulations and circuit-level measurements to validate and optimize standard cell performance.
• Perform detailed analysis of characterization data, identify deviations and anomalies, and propose corrective actions. Work closely with process engineers to understand and mitigate process variations that may impact standard cell library performance.
• Collaborate with the design automation team to enhance characterization methodologies and develop automation scripts for efficient library characterization. Participate in technology node evaluations and provide recommendations for standard cell library optimizations based on technology roadmaps.
• Collaborate with product development teams to ensure smooth integration and validation of standard cell libraries in advanced chip designs. Stay up-to-date with the latest advancements in FinFET technology, standard cell design methodologies, and industry trends.

Requirements

• Bachelor’s or Master’s degree in Engineering with a minimum of 10 years of experience in standard cell design. This includes setting up library characterization flows and methodologies, QA flows, circuit design, layout, and simulation, with a strong emphasis on FinFET technologies (e.g., 16nm, 12nm, 6nm, or below).
• Proficient in defining, characterizing, and executing custom digital and analog cells, low power management cells, level shifters, retention flops, GPIOs, and memories.
• Expertise in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence Virtuoso Liberate/LV/Mx/Trio, Virtuoso, ADE, Genus, Innovus and Tempus.
• Solid understanding of FinFET technology and its impact on standard cell library design and characterization. Experience in characterizing standard cell libraries for advanced process nodes is highly desirable.
• Knowledge of standard cell architecture, design rules, and layout considerations. Familiarity with circuit and layout design, static timing analysis (STA), Physical design and power analysis methodologies.
• Strong analytical skills and attention to detail for data analysis and problem-solving.
• Excellent programming and scripting skills (e.g., Python, Perl, Tcl) for automation and data processing tasks.
• Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days) while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 230 million units as of October 2023. For more information, visit www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

Responsibilities

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Specific responsibilities include:

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
• Develop test plans at block, sub-system, and chip level.
• Execute SoC-based verification at full-chip.
• Write C-based lib packages and tests.
• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
• Automating the test environment for randomized testing and scoreboarding.
• Utilize advanced debugging techniques to identify and resolve design and verification issues.
• Perform root-cause analysis and work with design teams to fix identified issues
• Define and track functional and code coverage metrics to ensure thorough verification.
• Ensure that verification quality meets or exceeds industry standards and project requirements.
• Edge-based AI inference is preferred.

Requirements

What you need to have to be successful

• BSEE /MSEE 5-8 years Degree of experience in block, sub-system, and full-chip verification
• Should have delivered multiple chips functioning to Specification.
• Identify and manage verification deliverables, milestones, and schedules.
• Proactively identify potential verification risks and develop mitigation strategies.
• Collaborate with design, architecture, and software teams to understand and verify design intent.
• Communicate verification progress, issues, and results to stakeholders and management.
• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges
• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
• C-based verification in an SoC environment is required
• Experience with ARM processor-based designs and low-power design techniques is a plus.
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
• Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5
• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 250 million units by 2024. For more information, visit?www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

Scope

The Timing Lead Engineer will plan and lead timing-related activities for Ambiq’s next-generation technology development. This will include defining signoff criteria, analyzing, developing design methodology, and managing tape-outs day-to-day driven by Ambiq’s Advanced Development team. The lead will work closely with other members of the Advanced Development team and the broader engineering community at Ambiq to develop and deploy Timing signoff-related flows and methodologies to support production chip development.

The successful candidate will be comfortable working both independently and in a leadership position, collaborating with a variety of senior engineers. The successful candidate will also be comfortable with the uncertainty of new methodology development and have a strong sense of independent drive.

Specific Responsibilities

• Define and own SoC timing signoff criteria, process corners, derates, uncertainties, and their tradeoffs. Be responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.
• Define and own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs. Drive clock tree planning and implementation for SoCs to achieve best energy, performance, and area.
• Be responsible for synthesis, PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions. Work with product development teams to rapidly deploy timing related methods in products.
• Plan and lead timing and other related activities for test chips owned by the Advanced Development team. As part of this effort, lead a small group of internal and/or contract resources.
• Maintain a relationship with and collaborate with 3rd party CAD tool vendors and fab during the development of new flows and methodologies. Validate and refine new techniques as part of a team that is building complex test chips in advanced FinFET nodes.

Requirements

• A bachelor’s or master’s degree in electrical engineering or a related field is required.
• Minimum 10 years of experience of hands-on experience in Static Timing Analysis, flows and methodologies for timing closure and have a strong understanding of noise, crosstalk, and OCV effects, aging, HTOL, soft errors in advanced FinFET nodes (16nm, 12nm, 7nm, 5nm)
• Proficient in Synthesis, place and route, UPF, Power integrity and reliability signoffs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
• Experience with large design STA and Timing Closure. Familiar with ECO techniques and implementation. Experience with STA signoff constraint authoring for full-chip level, tape-out signoff requirements, checklists, and associated automation.
• Experience in Cadence EDA tools (e.g., Genus, Innovus Tempus).
• Experience developing new technologies and transitioning those technologies to production is highly desirable. Familiar with important aspects of timing of SoC designs in bulk and FinFET technologies.
• Good programming skills with Perl and TCL.