Total 14 product engineer job vacancies in Singapore

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

• Requires a BS in Electrical or Computer Engineering
• Some years of relevant experience is preferable
• Fresh graduates are encouraged to apply

• You are responsible to drive and manage the silicon Bump & package assembly suppliers, backend processes and solutions to achieve the aggressive TQRDCEB goals.
• You will work closely with package design & technology, test & product engg, production planning, quality engg & NPI teams, assembly/substrate suppliers to support new product & technology introduction activities by defining processes, monitoring systems, manage process improvements and changes.
• Provide day-to-day support to bump and assembly suppliers & internal planning, product and test engineering teams.
• Plan, drive & implement improvement activities for continual improvement, 2nd sourcing, cost reduction & customer satisfaction.

Qualifications:

• PhD / Master / Degree in Mechanical / Electrical / Electronics Engineering with 7~12 years of relevant experience of managing advanced node silicon bumping, large body single & multi-chip (2.1/2.5/3D) package assembly, substrate & back-end suppliers and processes.
• Hands on experience in Product Life-Cycle Management - creating & maintaining Bill of Material structure, Process Documentation, Process Change Notification etc.
• Good team player, result oriented individual, experienced in project management, failure analysis tools, techniques and TQM. Good analytical, problem-solving skills. Flexible and agile.
• Sound knowledge of applicable industry standards, quality systems, regulations, knowledge of prevailing and emerging silicon package & substrate technologies, bumping and assembly processes, materials and equipment.
• Able to communicate with internal team members & external partners in various geographic locations and may required to travel from time to time at short notice.
• Experienced AutoCAD user. Knowledge of silicon & PCB fabrication, board assembly processes, are an added advantage

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and > 5 years of related experience

We have an exciting position in the explosive growth area of Data Center Enterprise Storage. In this role you will be responsible for
developing the most advanced semiconductor devices to support stringent high capacity storage needs across all the top tier service
providers. Our IC R&D team is looking for an experienced physical design engineer to develop high speed custom analog/mixed signal
products for the storage industry. A qualified applicant would work closely with circuit design engineers to lay out high-speed custom analog
designs and develop mask layouts for customer products, as well as printed circuit board designs. You will join a cross-functional team
responsible for developing leading edge high-speed custom IC products that ultimately achieve high volume production.

Job Responsibilities
- Lay out high speed, high performance analog/mixed-signal custom integrated circuits
- Work directly with a team of engineers to determine floor plan, routing and I/O requirements
- Perform IC design rule and connectivity verification and drive products through mask release flows.
- Contribute to methodology improvements to increase layout and verification efficiency.
- Create reticle layouts, documentation, and PO’s to release products for mask build.
- Complete PCB layouts for test hardware.

Requirements/Qualifications should be:
- Bachelor's degree in Electrical Engineering (or related field)
- 5 years experience in custom analog IC physical design
- Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity
verification is preferred
- Experience using Cadence Virtuoso XL preferred
- Experience with Cadence Allegro for PCB layout preferred
- Familiarity with both analog and digital layout tools and flows, circuit design concepts and IC manufacturing processes desired
- Strong communication skills
- Understanding of silicon process technologies (CMOS and Bipolar) and device physics would be a plus.
- Proven analytical skills (application of math and physics to solve problems)
- Must be meticulous and demonstrate attention to detail.

• Create ATE (Advantest SmarTest PS1600 & EXA Scale) test program and integrate various test functions in test flow to support First Silicon bring up for wafer and package in NPI phase.
• Perform design validation/characterization/experiment on ATE across process, voltage, frequency and temperature. Evaluate test and product margins, debug and communicate result/yield/analysis to various teams.
• Utilize ATE test tools and other test instrument to debug and analyze the test, design and product issue.
• Support ATE test hardware design (Including build instruction, SI/PI...etc.) and debug.
• Support test time reduction.
• Support proto demands/qualification for IP owner and customer requests.
• Complete test development, test program transfer and product release at respective milestones.
• Initiate, plan and execute multiple projects to achieve target.
• Good knowledge of product engineering, failure analysis and manufacturing test process.
• Interest in learning, researching, sharing and implementing new technology and test methodology.
• Good written/Oral communication skills.
• Result orientated and team work.

• You are responsible to drive and manage the silicon Bump & package assembly suppliers, backend processes and solutions to achieve the aggressive TQRDCEB goals.
• You will work closely with package design & technology, test & product engg, production planning, quality engg & NPI teams, assembly/substrate suppliers to support new product & technology introduction activities by defining processes, monitoring systems, manage process improvements and changes.
• Provide day-to-day support to bump and assembly suppliers & internal planning, product and test engineering teams.
• Plan, drive & implement improvement activities for continual improvement, 2nd sourcing, cost reduction & customer satisfaction.

Qualifications:

• PhD / Master / Degree in Mechanical / Electrical / Electronics Engineering with 7~12 years of relevant experience of managing advanced node silicon bumping, large body single & multi-chip (2.1/2.5/3D) package assembly, substrate & back-end suppliers and processes.
• Hands on experience in Product Life-Cycle Management - creating & maintaining Bill of Material structure, Process Documentation, Process Change Notification etc.
• Good team player, result oriented individual, experienced in project management, failure analysis tools, techniques and TQM. Good analytical, problem-solving skills. Flexible and agile.
• Sound knowledge of applicable industry standards, quality systems, regulations, knowledge of prevailing and emerging silicon package & substrate technologies, bumping and assembly processes, materials and equipment.
• Able to communicate with internal team members & external partners in various geographic locations and may required to travel from time to time at short notice.
• Experienced AutoCAD user. Knowledge of silicon & PCB fabrication, board assembly processes, are an added advantage

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

• Requires a BS in Electrical or Computer Engineering
• Some years of relevant experience is preferable
• Fresh graduates are encouraged to apply

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and > 5 years of related experience

Skills and responsibilities:

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 2 years or more experience in a relevant field.

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

• Requires a BS in Electrical or Computer Engineering
• Some years of relevant experience is preferable
• Fresh graduates are encouraged to apply

• Develop ATE test program, test hardware and bench evaluation board for analog, digital and power semiconductor devices.
• Research new test methodology for better test coverage and test time reduction.
• Work with multi-functional team to meet new product release schedule
• Proficiency in C++ Programming
• Degree in Electrical/Electronics Engineering
• Fresh graduates with good academic result are welcome to apply.

Skills and responsibilities:

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 5 years or more experience in a relevant field.

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and > 5 years of related experience

Be part of a worldwide R&D team in designing leading edge optocoupler products from Broadcom.

• Design analog and mixed signal ICs for industrial and automotive applications.
• Work with marketing and project team in defining specifications and system architecture to meet customer requirements.
• Perform circuit analysis, simulation and design verification with Cadence tools.
• Test and troubleshoot circuit problems to fix bugs.
• Customer support on IC failure analysis.
• Support reliability and manufacturing tests for product qualification.

Requirements

• Knowledge and experience in analog and mixed signal IC design.
• Familiarity with sigma delta converter, switched capacitor filter, bandgap reference, PLL/DLL, optical transceiver and power management design will be added
• advantages.
• Bachelors and 7+ years of related experience or Masters degree and 5+ years of related experience or PhD and 3+ years of related experience
• Master's or Bachelor's degree in electrical engineering