Total 25 telecommunication engineer job vacancies in Singapore

• Develop ATE test program, test hardware and bench evaluation board for analog, digital and power semiconductor devices.
• Research new test methodology for better test coverage and test time reduction.
• Work with multi-functional team to meet new product release schedule
• Proficiency in C++ Programming
• Degree in Electrical/Electronics Engineering
• Fresh graduates with good academic result are welcome to apply.

Skills and responsibilities:

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 2 years or more experience in a relevant field.

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

• Requires a BS in Electrical or Computer Engineering
• Some years of relevant experience is preferable
• Fresh graduates are encouraged to apply

Skills and responsibilities:

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 5 years or more experience in a relevant field.

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and > 5 years of related experience

Be part of a worldwide R&D team in designing leading edge optocoupler products from Broadcom.

• Design analog and mixed signal ICs for industrial and automotive applications.
• Work with marketing and project team in defining specifications and system architecture to meet customer requirements.
• Perform circuit analysis, simulation and design verification with Cadence tools.
• Test and troubleshoot circuit problems to fix bugs.
• Customer support on IC failure analysis.
• Support reliability and manufacturing tests for product qualification.

Requirements

• Knowledge and experience in analog and mixed signal IC design.
• Familiarity with sigma delta converter, switched capacitor filter, bandgap reference, PLL/DLL, optical transceiver and power management design will be added
• advantages.
• Bachelors and 7+ years of related experience or Masters degree and 5+ years of related experience or PhD and 3+ years of related experience
• Master's or Bachelor's degree in electrical engineering

Minimum qualifications:

• Bachelor’s degree in electrical engineering, or an engineering field.
• 10 years of experience as a Semiconductor IC, Quality, Reliability or Product Engineer.
• Experience in a technical team and/or people management.
• Experience with quality control, test coverage, and IC qualification.

Preferred qualifications:

• Over 10 years of experience in quality/reliability and semiconductor IC technology.
• Experience with semiconductor suppliers and manufacturing and supply chain processes.
• Experience in troubleshooting on different failure mode and root cause analysis.
• Experience with IC qualification, data review, and production release.
• Technical expertise of materials and processes for semiconductor ICs.

Background:

• Good understanding of materials, physical failure analysis and measurement techniques.
• Familiar with ISO 9001 or other quality management standards
• Able to work in a diverse team, use proactive approach, self-reliant & excellent decision-making skills.
• Capable of supplier, customer, and stakeholder management.

Responsibilities:

• Quality and reliability expert with a track record of improving the quality of semiconductor ICs during New Product Introduction (NPI) as well as the product life-cycle.
• Establish and be responsible for the quality and reliability throughout the product/IC life cycle.
• Work with cross-functional teams to define and ensure processes in place to provide the data required to manage quality and reliability.
• Interface with suppliers on a regular basis to track and drive root cause, resolve issues, track return material authorizations, corrective actions (OCAPs), and failure analysis.
• Work with suppliers and SMEs to provide material waivers including assessment, documentation, and protocols.
• Drive supplier process audits, product audits, 8D reports and summarize results for Exec Management as well as Global Operations team.
• Technical support of Global operations team for continuous improvement initiatives, as well as qualification and application of ICs.
• Travel up to 25%.

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 3 to 4 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 5 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.

• Create ATE (Advantest SmarTest PS1600) test program and integrate various test functions in test flow to support First Silicon bring up for wafer and package in NPI phase.
• Perform design validation/characterization/experiment on ATE across process, voltage, frequency and temperature. Evaluate test and product margins, debug and communicate result/yield/analysis to various teams.
• Utilize ATE test tools and other test instrument to debug and analyze the test, design and product issue.
• Support ATE test hardware design/debug and test time reduction.
• Support proto demands/qualification for IP owner and customer requests.
• Complete test development, test program transfer and product release at respective milestones.
• Initiate, plan and execute multiple projects to achieve target.

Requirements

• Bachelor or Master’s degree in Electronics, Electrical, Computer Engineering or relevant disciplines.
• Minimum 3 years of hands-on experience in ATE test program development i.e. Teradyne UP1600 or Advantest PS1600.
• Self-motivated. Able to plan, execute and deliver within given timeline.
• Strong team player with creativity, critical thinking, problem-solving ability and excellent communication skills.
• Good knowledge of product engineering, failure analysis and manufacturing test process.
• Interest in learning, researching, sharing and implementing new technology and test methodology.
• Good written/Oral communication skills.
• Result orientated and team work.

We have an exciting position in the explosive growth area of Data Center Enterprise Storage. In this role you will be responsible for developing the most advanced semiconductor devices to support stringent high capacity storage needs across all the top tier service providers. Our IC R&D team is looking for an experienced physical design engineer to develop high speed custom analog/mixed signal products for the storage industry. A qualified applicant would work closely with circuit design engineers to lay out high-speed custom analog designs and develop mask layouts for customer products, as well as printed circuit board designs. You will join a cross-functional team responsible for developing leading edge high-speed custom IC products that ultimately achieve high volume production.

Job Responsibilities

• Lay out high speed, high performance analog/mixed-signal custom integrated circuits
• Work directly with a team of engineers to determine floor plan, routing and I/O requirements
• Perform IC design rule and connectivity verification and drive products through mask release flows.
• Contribute to methodology improvements to increase layout and verification efficiency.
• Create reticle layouts, documentation, and PO’s to release products for mask build.
• Complete PCB layouts for test hardware.

Requirements/Qualifications:

• Bachelor's degree in Electrical Engineering (or related field)
• Minimum 8 years experience in custom analog IC physical design
• Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is preferred
• Experience using Cadence Virtuoso XL preferred
• Experience with Cadence Allegro for PCB layout preferred
• Familiarity with both analog and digital layout tools and flows, circuit design concepts and IC manufacturing processes desired
• Strong communication skills, proficiency in both oral and written English
• Understanding of silicon process technologies (CMOS and Bipolar) and device physics would be a plus
• Proven analytical skills (application of math and physics to solve problems)
• Must be meticulous and demonstrate attention to detail.

Enterprise End-user Services (EES) organization of Broadcom Global IT is a technology forward organization constantly scanning the industry for new innovative solutions to implement. The team of highly motivated individuals do not shy away from exploring, testing and introducing leading edge technology that will both increase efficiencies and enhance end-user experiences. With Cloud First tenet as our guiding principles, Broadcom Global IT implements leading edge new technology and services that increases the effectiveness and efficiencies of the workforce.

The team is looking for an individual with strong IT client services skills (PC and Mac) who thrives on working in a global environment with a broad range of people including vendors, support personnel, and end users. This individual will join a team of dedicated Global IT members to deliver client services to Broadcom users. A degree in Information Technology or Engineering with a minimum of 3 years IT Support experience is desired.

This role will focus on developing, improving and standardizing client services solutions for PC imaging and site support (including on premise and remote locations). In addition, the role will require the individual to investigate creating technical solutions based on weekly/monthly trend analysis of client services issues reported to the Broadcom service desk.

Utilizing the experience gained in developing client services solutions, this individual will also be responsible for creating knowledge and self-help articles with a primary focus on client services solutions for the IT KnowledgeBase (KB) using the Broadcom ITSM tool (currently on the Wolken platform).

This position is based in Singapore and will report directly to the Identity & Services Technology Sr. Manager.

Overall Required Skills/Attributes:

• Knowledge of the Broadcom standard PC Environment (training may be provided as required)
• Must understand and communicate difficult concepts and provide instructions in a clear and straightforward manner.
• Must be able to document work for effective future maintenance.
• Must be able to work and communicate effectively in a team environment, yet able to complete tasks individually.
• Must be able to establish and maintain protection of sensitive data and resources with appropriate safeguards in accordance with policy and legal requirements
• Must facilitate creation of appropriate records required for service continuity and performance evaluation.
• Ability to effectively deliver and meet the customer’s expectations
• Ability to work with Outsourced onshore and offshore partners to deliver resolutions
• Ability to meet targeted response time (SLA)
• Ability to work in a fast moving self-driven team with minimal supervision
• Effective communicator who can articulate to all levels
• Motivation, confidence and passion is a must including an eye for details and follow through
• Minimal supervision with the ability to prioritize and manage time if workload is high.
• Ability to work successfully in a fast-paced team environment.
• Team player.
• Enthusiastic and ready to chip in when needed.
• Experience in managing outsource partners is preferred.
• Prior employment in a company of similar size, culture and organization will be helpful.
• Prepared to work in a Global Team (evening/night time conference calls is a norm).
• Willing to put in extra hours during major projects.
• Some travel required (anticipated <10%)

Client Services Knowledge Management - Responsibilities:

• Design and enforce standard template and formatting to be used across all knowledge articles.
• Introduce marketing strategies (with internal IT) to promote the use of Knowledge Base.
• Engage with knowledge contributors to ensure addition, changes and removal of articles in a timely manner. Knowledge contributors include the Service Managers, Support Teams, Process Managers or even End Users.
• Work closely with the Tools Team to optimize out-of-the-box features of the ITSM tool.
• Work closely with the Communications team and Internal Portal team to ensure the IT Knowledge Base is in-sync and integrates seamlessly with IT communications and IT Portal.
• Engage Information Security team to ensure published knowledge is within security guidelines.
• Plan and prepare Knowledge Base for M&A (Merger & Acquisition) changes (i.e. knowledge related to site moves, service transition, service retirement)
• Work with the Chatbot Services team to constantly review and improve gap areas in content to improve end-user self-service via chatbot.

Client Services Knowledge Management - Required Skills / Attributes:

• At least 2 years experience in Knowledge Management.
• Good command of written English.
• Excels in writing simple and concise instructions.
• High-level knowledge of all IT Services.
• Enjoys helping others help themselves.
• Capable of reviewing and enhancing articles written by others.
• Good interpersonal skills.
• Able to quickly understand new services/concepts.
• Experience working on the Wolken platform will be an added advantage.
• Base knowledge of chatbot services and how knowledge content is utilized by LLMs to provide chatbot answers.

Client Services Solutions Engineering - Responsibilities:

• PC Client imaging:
  Gain deep technical expertise in the Broadcom PC imaging solution
  Work closely with vendors providing imaging development, management and maintenance
  Manage image updates – image “recipe” and deployment/update schedule
  Ensure image is tested on all Broadcom standard hardware models
  Ensure image is deployed to the global site support staff and partners including performing necessary updates to imaging guides
  Deep technical support for Broadcom Service Desk and global client support staff for PC hardware and imaging issues.
  Design and implement new deployment solution (like PXE boot) for PC imaging
• Gain deep technical understanding of the Broadcom Standard Client Hardware and Software support model and implement/improve solutions where possible.
• Perform weekly reviews of the service desk top ticket drivers in the client services area and identify and implement solutions where possible.
• Work with communications and webinars team to develop materials related to critical experience changes for users
• Additional client services, projects and deliverables as assigned.

Client Services Solutions Engineering - Required Skills / Attributes:

• Strong knowledge of:
  DHCP & DNS
  AD (Active Directory)
  Wireless & Wireless Hotspots
  Printers
  Snooping/Virus
  Dell Clients & peripherals
  MacBook Air & MacBook Pros
  Windows 11 and Apple OSX operating system
  MS Outlook (limited transition support only)
  Mobile devices (iPhone – iOS & Samsung Sx Android)
  Symantec antivirus
  Workspace One SW distribution
  Windows patch updates
  Broadcom Standard Browsers – Chrome, Firefox, IE & Safari
  Windows Print
  Client Network configuration – Client firewall, Wi-Fi and other system configurations
• Very helpful for Incumbent to have knowledge and experience with:
  Broadcom Standard Clients support
  Broadcom Collaboration Services – Google Enterprise Apps, BOX, Video, Zoom & Zoom Conference
  Single-sign On (OKTA)
  Experience with Broadcom Standard Office software & applications (ex: MS Office, Zoom client & Browsers – Chrome, Safari, Firefox, etc).

Foundation IP Design Engineer

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and 5 years of related experience

Job Description

Foundation IP Design Engineer

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS degree in Electrical or Computer Engineering

Foundation IP Design Engineer

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS degree in Electrical or Computer Engineering with 2 years of related experience

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D-D/A converters (ADC & DAC). You will be part of a worldwide R&D team developing high-performance package designs for ASICs used in artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 112G and higher, RF/Microwave ADC/DAC, DDR and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design.

RESPONSIBILITIES:

• Overall design responsibility for ASIC package designs (layout/routing), including aspects of impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across multiple projects simultaneously
• General flip-chip BGA package design & engineering

EDUCATION/EXPERIENCE & REQUIREMENTS:

• B.Eng (EE/EEE) or similar field and 5+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• M.Eng (EE/EEE) or similar field and 3+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers.
• Good organizational and task management skills to manage multiple package design projects.

PREFERRED EDUCATION/EXPERIENCE & REQUIREMENTS:

• B.Eng (EE/EEE) or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes preferred.
• M.Eng (EE/EEE) or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes preferred.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

- BS degree in Electrical or Computer Engineering

R&D engineer position available in design and physical implementation of high performance System-On-Chip ASICs.

• Key competencies required are: Working experience leading team in physical design implementation of large ASICs (100 to 400 million gates complexity).
• Demonstrated ability in providing technical support to customers and managing customer working relationship.
• Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
• In-depth CPU architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.

Utilize commercial and in-house EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm process technologies.

Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products

Qualifications / Requirements

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 5 years or more experience in a relevant field.
• Familiarity with one or more VLSI design tools for Place&Route, Verilog Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
• Experience in Perl & Tcl Scripting languages 3. Proficiency in UNIX/Linux is advantageous.

• Create ATE (Advantest SmarTest PS1600) test program and integrate various test functions in test flow to support First Silicon bring up for wafer and package in NPI phase.
• Complete test development, test program transfer and product release at respective milestones.
• Perform design validation/characterization/experiment on ATE across process, voltage, frequency and temperature. Evaluate test and product margins, debug and communicate result/yield/analysis to various teams.
• Support proto demands/ramp, qualification IP owner and customer requests.
• Utilize ATE test tools and other test instrument to debug and analyze the test, design and product issue.
• Support ATE test hardware design/debug and test time reduction.
• Initiate, plan and execute multiple projects to achieve target.
• Good knowledge of product engineering, failure analysis and manufacturing test process.
• Interest in learning, researching, sharing and implementing new technology and test methodology.
• Good written/Oral communication skills.
• Result orientated and team work.

• Product engineering for VCSEL products
• Maintaining and improving VCSEL performance, yield, and reliability with extensive data analysis
• Ph.D. in physics, electrical engineering, material science or equivalent
• Experience in crystal defect study of semiconductor material with TEM a plus
• Successful candidate must be willing to work in Depot Road

• You are responsible to drive and manage the silicon Bump & package assembly suppliers, backend processes and solutions to achieve the aggressive TQRDCEB goals.
• You will work closely with package design & technology, test & product engg, production planning, quality engg & NPI teams, assembly/substrate suppliers to support new product & technology introduction activities by defining processes, monitoring systems, manage process improvements and changes.
• Provide day-to-day support to bump and assembly suppliers & internal planning, product and test engineering teams.
• Plan, drive & implement improvement activities for continual improvement, 2nd sourcing, cost reduction & customer satisfaction.

•Qualifications:

• PhD / Master / Degree in Mechanical / Electrical / Electronics Engineering with 7~12 years of relevant experience of managing advanced node silicon bumping, large body single & multi-chip (2.1/2.5/3D) package assembly, substrate & back-end suppliers and processes.
• Hands on experience in Product Life-Cycle Management - creating & maintaining Bill of Material structure, Process Documentation, Process Change Notification etc.
• Good team player, result oriented individual, experienced in project management, failure analysis tools, techniques and TQM. Good analytical, problem-solving skills. Flexible and agile.
• Sound knowledge of applicable industry standards, quality systems, regulations, knowledge of prevailing and emerging silicon package & substrate technologies, bumping and assembly processes, materials and equipment.
• Able to communicate with internal team members & external partners in various geographic locations and may required to travel from time to time at short notice.
• Experienced AutoCAD user. Knowledge of silicon & PCB fabrication, board assembly processes, are an added advantage

• R&D engineer position available in design and physical implementation of high performance System-On-Chip ASICs.

1. Key competencies required are: Working experience leading team in physical design implementation of large ASICs (100 to 400 million gates complexity).
2. Demonstrated ability in providing technical support to customers and managing customer working relationship.
3. Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
4. In-depth CPU architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.

• Utilize commercial and in-house EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm process technologies.
• Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products

Qualifications :

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 5 years or more experience in a relevant field.
• Familiarity with one or more VLSI design tools for Place&Route, Verilog Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
• Experience in Perl & Tcl Scripting languages 3. Proficiency in UNIX/Linux is advantageous.

Broadcom Central Engineering is looking for a qualified individual who can provide best-in-class development and support for Analog/Mixed Signal tool flows focused on advanced FINFET process nodes. This individual will be hands-on, heavily involved in day-to-day design/layout issues and in addition, interact with EDA vendors, the PDK development and process technology teams to provide timely solutions, and develop, maintain, and support utilities to improve productivity. If hired, the candidate is expected to be physically located in Broadcom's Singapore facility.

Responsibilities:

The candidate's main responsibilities include the following:

• Support (50%), enhance, and maintain PDKs and various Analog/Mixed-Signal design tools
• Develop software for automation in Skill, Perl, Unix Shell scripting
• Create documentation and provide hands-on training for design and layout engineers
• Work with EDA vendors to track and resolve issues
• Work with Technology Foundry teams (external/internal) to facilitate debugging and proper characterization of all tool related issues.

Requirements:

• Master in Electrical Engineering or Computer Science + 5 years of EDA experience.
• Expertise in the following CAD Tools: Virtuoso Studio 23.1, Cadence ADE-L/XL, Maestro, Spectre, Virtuoso Layout, Quantus QRC, Voltus-Fi APS/EMIR, EMX, and Synopsys Hspice, Primesim, StarRC, Quickcap, and Mentor Calibre/PERC
• Solid background in programming skills, circuit design, and device physics knowledge to help solve circuit design, layout, physical verification, and post-layout extraction challenges and problems. Looking for domain expertise/specialists in RCX, EM/IR , Substrate-Noise/Crosstalk and Aging/SHE circuit-simulation.
• Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation
• Expert in Cadence Skill, Perl, Unix Shell and utilities
• Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to detail, and the ability to work well in a team

• Accountable for the performance for a range of assigned production machines. To analyze systematically and uncover the root cause of any unscheduled failures and provide long term solutions to eliminate/reduce them.
• Able to perform independent hands-on troubleshooting and ability to direct team or single-handedly return machine back to day one condition in a timely manner.
• Train & guide Associate Engineers and Junior Engineers on the technical aspects of the machines. Specify and improve preventive and predictive measures to reduce unscheduled downtimes.

Preferences:

• Self driven and motivated to continuously learn and grow his/her machine related technical abilities. Able to work under pressure.
• In depth experiences in some of these areas: repair of semiconductor grade CVD (chemical vapour deposition) machines, RF heating. Knowledge in vacuum systems, fluid & thermodynamics, system controls, material science.
• To continually review and upgrade preventive/predictive maintenance to improve machine performance.
• Able to do programming in PLC or other platforms is advantageous

Qualifications

• Minimum Bachelor of Engineering in Electrical or Mechanical Engineering.
• Minimum 5 years working experience in machine design and equipment support.
• Job level will depend on the number of years of relevant working experience

• Create ATE (Advantest SmarTest PS1600) test program and integrate various test functions in test flow to support First Silicon bring up for wafer and package in NPI phase.
• Complete test development, test program transfer and product release at respective milestones.
• Perform design validation/characterization/experiment on ATE across process, voltage, frequency and temperature. Evaluate test and product margins, debug and communicate result/yield/analysis to various teams.
• Support proto demands/ramp, qualification IP owner and customer requests.
• Utilize ATE test tools and other test instrument to debug and analyze the test, design and product issue.
• Support ATE test hardware design/debug and test time reduction.
• Initiate, plan and execute multiple projects to achieve target.
• Good knowledge of product engineering, failure analysis and manufacturing test process.
• Interest in learning, researching, sharing and implementing new technology and test methodology.
• Good written/Oral communication skills.
• Result orientated and team work.