Total 2 art design job vacancies in D23 Hillview, Dairy Farm, Bukit Panjang, Choa Chu Kang

Position Overview:

The Senior/Staff Design Engineer will be responsible for developing micro-architecture for ISP and CV related algorithms, utilizing RTL design using Verilog/System Verilog coding and HLS tools like Catapult. They will analyze metrics such as power, performance, and area to meet key objectives, collaborate with architects and DV Engineersfor efficient verification signoff, and support FPGA tasks such as emulation,validation, and debugging.

Responsibilities:

• Develop micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Analyze and optimize metrics like power, performance, and area.
• Cooperate with verification architects and DV engineers to ensure high quality IP delivery.
• Support backend team for SoC signoff.
• Oversee FPGA tasks including emulation, validation, and debugging.

Qualification/Requirements:

• Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
• Experience: Minimum 5yearsand aboveof experience in ASIC design. Expertise in image signal processing projects is beneficial.
• Technical Skills:
• - Advanced proficiency in HDL languages (Verilog, System Verilog).
• - In-depth knowledge of all phases of ASIC frontend design and sign-off.
• - Extensive experience in image/vision/video data processing or algorithm acceleration.
• - Proficiency in scripting languages like Python, Perl, or C/C++.
• Soft Skills: Excellent leadership, teamwork, and communication skills.
• Additional Notes:Stronganalytical skills and the ability to lead complex projects independently and within teams.

Position Overview:

Black Sesame Technologies is looking for enthusiastic fresh graduates to join our team as Design Engineers. We’re excited to expand our campus hiring plan for 2025 and are seeking candidates who are eager to dive into the world of ASIC design and contribute to cutting-edge technology.

Responsibilities:

• Assist in designing micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Support the analysis of metrics related to power, performance, and area.
• Collaborate with architects and DV Engineers to ensure efficient verification signoff.
• Help with FPGA tasks, including emulation, validation, and debugging.

Qualification/ Requirements:

• Education: Minimum Master’s degree and above in Electrical/Electronics/Computer Engineering.
• Experience: Entry-level position; relevant coursework or project experience in ASIC design or image signal processing is a plus.

Technical Skills:

o Experience/knowledge in Verilog/SystemVerilog and C/C++.

o Familiarity with ASIC design processes and frontend design.

o Knowledge of image/vision/video data processing or algorithm acceleration is beneficial.

o Familiarity with scripting languages (Python, Perl, Tcl) is a plus.

Soft Skills: Strong teamwork and communication skills.

Additional Notes: Strong analytical skills and a willingness to learn and adapt in a dynamic environment.