Total 13 job vacancies by Ethos Tech One Pte. Ltd.

Key Responsibilities

• Validate the latest SerDes design including PMA4 224G transceiver on the most advance technology node
• SerDes debug with designers on Silicon
• Tuned the latest design to performance at the most optimum setting
• Use the latest simulation tools and measuring equipments

Requirements

• Masters/PhD degree in Electrical/Microelectronics Engineering or related field
• Experience with RF Analysis Tool : Cadence Suite, Keysight ADS and MATLAB Simulink
• Extensive experience with common lab equipment including Oscilloscope, Spectrum Analyzer, VNA/ PNA-X for high-speed data links
• Strong programming/scripting skills coding languages such as Python, Signal Studio and Keysight VSA89600
• Knowledge of Electromagnetic theory, transmission line theory, passive/ active model extraction methodology, antenna-package-front-end interface co-design, RF front-end blocks.

Job Description

• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience with designing with FPGA using Vivado is a plus

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience with designing with FPGA using Vivado is a plus

Job Description

• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience with designing with FPGA using Vivado is a plus

Job Description

• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience with designing with FPGA using Vivado is a plus

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience with designing with FPGA using Vivado is a plus

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience with designing with FPGA using Vivado is a plus

Job Description

• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Job Description

• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Job Description

• Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Floor Planning, Synthesis, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills