Total 36 supply chain engineer job vacancies in Singapore

What you will do

• Responsible for standard cell test key design of leading-edge process node (4nm/3nm/2nm), from schematic netlist to gds.
• Work with layout engineer for test key implementation and physical verification including DRC/LVS/ERC/ANT.
• Perform layout extraction, simulation, testing data collection and processing.
• Analyze simulation and silicon data including performance, power correlation, big data analysis, AI model training.
• Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
• Develop advanced library generation methodology and flow, including timing & power characterization, kit generation, regression, and quality assurance, involved with data analysis and machine learning as well.

What you bring

• BS/MS in Electrical and Electronic Engineering/Computer Engineering/Computer Science with minimum 8 years(MS) or 10 years(BS) industry experience.
• Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
• Experience of test chip design in FinFet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
• Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
• Strong communication and teamwork skills to collaborate effectively with cross-functional teams.

Location: One North, Singapore

What you will do

• CPU Testing Binning Strategy & Realization
• Production volume ramp-up support which includes fast-turn-around test program delivery/optimization and cost reduction through yield optimization and test time reduction
• Cross collaboration with Design/DFT/DV/TE team to enable efficient test-case simulation and (mini)ATE bring-up

What you will bring

• Bachelor/Masters Degree in Electrical/Computer Engineering
• Min 3 years of CPU related Chip Mass Production Experience is a MUST.
• Software+Hardware Testing PCB built
• Familiarity with CPU Testing (ARM/MIPS/SNPS...)
• Cross-site working experience is a MUST.
• Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.
• Smart-Phone Adv. ASIC consumer product HW design experience is a PLUS.

Location: One North, Singapore

What you will do

[Physical Design]

• Work for physical design and development activities of MediaTek’s Ghz ARM-based microprocessors
• Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and
• Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing and power optimization

[STA/Power Signoff]

• Involve in activities encompass Static Timing Analysis on advanced process nodes (28nm, 20nm, 16nm & beyond)
• Technical disciplines include STA, and analysis of complex and timing-critical microprocessor
• Work closely with RTL function designers and physical designers to optimize design components such as timing and power
• Design Methodology (1):
• This position is in charge of design methodology from RTL-Synthesis-DFT-PNR-STA-PI.
• Specific skill set is: able to boost productivity using either programming or EDA solution
• AI learning Programming is a big plus

What you will bring

• Bachelor/Masters Degree in Electrical and Electronic Engineering/Computer Engineering
• Good with concept of digital design
• Good with communication, team work and scripting skills
• Understanding of RTL2GDS flow is a plus

Location: One North, Singapore

What you will do

• CPU Testing Binning Strategy & Realization
• Production volume ramp-up support which includes fast-turn-around test program delivery/optimization and cost reduction through yield optimization and test time reduction
• Cross collaboration with Design/DFT/DV/TE team to enable efficient test-case simulation and (mini)ATE bring-up

What you will bring

• Bachelor/Masters Degree in Electrical/Computer Engineering
• Min 7 years of CPU related Chip Mass Production Experience is a MUST.
• Software+Hardware Testing PCB built
• Familiarity with CPU Testing (ARM/MIPS/SNPS...)
• Cross-site working experience is a MUST.
• Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.
• Smart-Phone Adv. ASIC consumer product HW design experience is a PLUS.

Location: One North, Singapore

What you will do

[Physical Design]

• Work for physical design and development activities of MediaTek’s Ghz ARM-based microprocessors
• Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and
• Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing and power optimization

[STA/Power Signoff]

• Involve in activities encompass Static Timing Analysis on advanced process nodes (28nm, 20nm, 16nm & beyond)
• Technical disciplines include STA, and analysis of complex and timing-critical microprocessor
• Work closely with RTL function designers and physical designers to optimize design components such as timing and power
• Design Methodology (1):
• This position is in charge of design methodology from RTL-Synthesis-DFT-PNR-STA-PI.
• Specific skill set is: able to boost productivity using either programming or EDA solution
• AI learning Programming is a big plus

What you will bring

• Bachelor/Masters Degree in Electrical and Electronic Engineering/Computer Engineering
• Good with concept of digital design
• Good with communication, team work and scripting skills
• Understanding of RTL2GDS flow is a plus

Location: One North, Singapore

What you do:

• Generative AI: Language/Multi-modal Model Algorithm Development
  - Transformer-based architecture (LLaMa etc.)
  - RNN and SSM-based architecture (Mamba etc.)
• AI Vison/Voice/NLP/Algorithm Development
• Edge AI (APU) Algorithm Development and Optimization
  - Neural network optimization (Quantization/Pruning/Speculative Decoding)
  - Neural network design automation
• Advanced AI Algorithm: Reinforcement learning (RL), On-device learning

What you bring:

• Familiar with deep learning framework: Tensorflow, Pytorch.
• Familiar with on-device framework for mobile/embedding devices: TFLite, ExecuTorch
• Required programming language: Python, C/C++, Java.
• 2+ years experience in deep learning and generative AI algorithm/model development/optimization, model training methodology.
• It is nice to have experience in developing deep learning and generative AI algorithms for mobile/embedding devices.
• Candidates with more years of experience will be considered for a senior role.

Overview

We are looking for result-driven candidates who would thrive under a fast-pace working environment and having a strong desire to make an impact in their organization.

What you will do

• Own the entire layout implementation process: schedule estimation, floorplanning, layout construction, physical verification and memory compiler leaf-cell creation
• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely with multi-functional members to optimize layout realization according to the desired power, performance and area optimization requirement
• Candidates with strong soft skills could be tasked to undertake project management, coaching of new hires/interns or workflow improvement initiative

What you will bring

• Bachelor’s degree in Electrical/Electronic/Computer Engineering or equivalent
• At least 8~10 years of direct experience in custom Memory layout implementation (SRAM/ROM/TCAM/CIM) in advanced finFET/GAA process nodes
• Proficient in understanding DRM of advanced CMOS technologies and have a good understanding of deep sub-micron and DFM issues (eg. WPE, LOD effects, etc.)
• Strong knowledge in floor-planningtechniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integrationflow
• Strong knowledge in executing and debugging various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.
• Proficient in Synopsys/Cadence layout editors
• Ability in script programming (eg. Python, Tcl, Perl or C-shell) is a plus
• Team player and effective in cross-team communication and time management

Location: One North, Singapore

Why MediaTek

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Job Description:

• Perform CPU design integration and IP development for ARM based CPU subsystem.
• Derive and develop Application or Subsystem PPA (Performance, Power, Area) optimization initiatives.
• Support SoC in MCUSYS Subsystem from Technical Feasibility Evaluation phase to Post-Silicon debug phase.

Job Requirement:

• Bachelor's Degree/Master's Degree in Electrical/Computer Engineering.
• Min 10 years of CPU related Architect/ RTL/ Verification/ Implementation design experience.
• Familiarity with ARM/MIPS/SNPS ARC CPUs.
• Cross-site working experience is a MUST.
• Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.
• Smart-Phone Adv. ASIC consumer product HW design experience is a PLUS.

Responsibilities

• Responsible for physical design and development activities of MediaTek Ghz, AI processors and neural network DSP
• Involve in activities encompass physical design and analysis of complex and timing-critical AI processors and neural network DSP
  Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing, power optimization and physical verification
• Work closely with MediaTek colleagues in Taiwan and Singapore in implementation methodology co-development and flow deployment

Requirement

• Bachelor/Masters Degree in Electrical/Computer Engineering
• Min 2 years of high-speed CPU/GPU/DSP Subsystem RTL Integration experience or IP/Block/SoC Design experience (Candidate with less than 5 years of relevant experience will be considered for junior position)
• Experience with Synopsys ICC (preferred) or Cadence tools from netlists to GDS
• Experience in graphics processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification)
• Knowledge of high-speed/low power IP and custom circuit design
• Experience with power noise and reliability tools such as Redhawk and Voltus
• Good communication and scripting skills

Responsibilities:

• Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS.
• Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP.
• Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

Requirement:

At least 4 years of experience in Physical Design and Signoff

[Skills]

>> Synthesis::

PPA improvement through synthesis recipe exploration for better perf, power, and area.

>> Physical design ::

Floor Planning, Place & Route followed by Timing and Physical Closure

>> Signoff ::

PI : PG mesh spec selection, Bump/RDL planning, IR closure

PV : DRC, LVS, ANT, ERC closure

STA : Block level timing closure

Responsibilities:

• Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS.
• Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP.
• Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

Requirement:

At least 4 years of experience in Physical Design and Signoff

[Skills]

>> Synthesis:

PPA improvement through synthesis recipe exploration for better perf, power, and area.

>> Physical design :

Floor Planning, Place & Route followed by Timing and Physical Closure

>> Signoff :

PI : PG mesh spec selection, Bump/RDL planning, IR closure

PV : DRC, LVS, ANT, ERC closure

STA : Block level timing closure