Total 4 staff nurse job vacancies in D22 Jurong, Jurong Island, Tuas

Responsibilities

1. Develop design requirements of an NPU given system level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on in digital design experience is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.

Position Overview:

You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

1. Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog

2. Experience in ARM, RISC processor system

3. Experience in embedded C and assembly code programming

4. Experience in analysis of power, timing and area

5. Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)

6. Disciplined, quality-minded, and highly driven for excellence

7. Excellent team player and good communication skills

8. MSEE/BSEE in Electrical Engineering or Computer Engineering

9. Candidates with relevant experiences would be offered as Staff, taking on higher responsibilities

10. Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus

11. Experience in system modelling and simulation using emulator and SystemC is a plus

12. Passionate and strong in general programming is a plus

Position Overview:

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

1. Experience in UVM verification methodology

2. Disciplined, quality-minded, and highly driven for excellence,

3. Excellent team player and good communication skills

4. MSEE/BSEE in Electrical Engineering or Computer Engineering, with 3 years of relevant experience, but are open to fresh graduates with outstanding results

5. Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities

6. Experience in video processing and video analytics is a plus

7. Passionate and strong in general programming is a plus

We are looking for multiple seasoned Senior and Staff System Engineers to grow an Edge AI & Systems software team to the next level. This team works within the larger ASIC team to architect and enhance Neural Network solutions in the Video Processor roadmap including these current and older products:

• https://www.ovt.com/products/oax8000/
• https://www.ovt.com/products/oax4600/
• https://www.ovt.com/products/oa7100/

Deliveries:

• Neural Network Processor (NPU) architecture, programming Model, simulation, verification, profiling and optimization
• Specification, review and verification of other IP blocks
• FPGA images and IO boards for pre-silicon verification and design exploration
• Boot ROM, bare metal BSPs, sample applications

Responsibilities:

• Support Inference Engine, Toolchain and ASIC teams on NPU
• Constantly improve productivity through automation in all areas

Skills:

• Strong ANSI C bare-metal design, implementation, optimization and debugging using GCC-like toolchains
• Strong processor architecture knowledge: ARM/RISC-V ISA, symmetric multiprocessing, cache architecture, SIMD, Vector Processing, custom instructions
• Strong software, hardware and FPGA debugging capability
• Good communication, collaboration, task estimation & reporting, CI/CD via tools such as Confluence, Git, JIRA etc
• Familiarity with

o Python for prototyping, demo, verification and/or automation

o OS: GNU/Linux, proprietary RTOS, Bare metal

The following will be advantageous:

• Detailed and comprehensive understanding of TinyML (e.g. TensorFlow Lite for MCUs), from training, quantization through to operator execution, optimizing for power, performance, and size.

Requirements:

1. Ph.D/MSEE/BSEE in Electrical Engineering, Computer Science or Computer Engineering
2. At least 5 years of commercial embedded system architecture and development experience.