What you do

Be part of the team that validates the physical sign-off of our chips, powering the brands we love every year with 2 billion consumer electronic products such as digital TVs, home audio devices, DVD/Blue-ray players, smartphones, tablets, networking and connectivity products, and many more. As a member of the MediaTek Physical Verification Sign-off team, you will be responsible for ensuring the manufacturability and reliability of IC designs through rigorous physical verification processes to enable the success of our chips tape-out. Join us in shaping the future of technology and making a real impact on the world!

• Responsible for assembling of various design system into a full chip.
• Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.
• Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and schematic of the IC design.
• Execute electrical rule check (ERC) to identify potential electrical issues and ensure the integrity of the design.
• Perform antenna and electrostatic discharge (ESD) checks to prevent potential reliability, latch-up, leakage issues.
• Collaborate with design and layout teams to address and resolve physical design issues and optimize the layout for manufacturability and reliability.
• Contribute to the development and improvement of physical verification methodologies and flows.
• Work closely with process technology teams to understand and address process-related challenges and constraints.
• Participate in tape-out activities and ensure that the physical design meets the required quality and reliability standards for fabrication.

What you bring

• With minimum 8 years of relevant experience.tronic Engineering / Computer Science or equivalent..
• With minimum 8 years of relevant experience
• Solid understanding of physical design concepts, IC manufacturing processes, and semiconductor device physics.
• Proficiency in using physical verification tools such as Calibre, IC Validator, or other industry-standard DRC/LVS tools.
• Experience with scripting languages such as TCL, Perl, or Python for automation and tool customization.
• Strong problem-solving skills and the ability to analyze and debug complex physical design issues.
• Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
• Familiarity with EDA (Electronic Design Automation) tools and design methodologies is a plus.
• Proficient in UNIX (Linux) platforms.
• Strong communication skills, problem solving and analytical skills.

Location: One North, Singapore

Who We Are

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

At Cheil, we are passionate about ideas that move.

We believe that the right idea will move seamlessly across channels: from online to offline, above the line to below the line, in-store to out-of-home. It will move brands, move products and most importantly, move people. The right idea will move everything forward.

Established in 1973 with headquarters in Seoul, South Korea, Cheil Worldwide is one of the world’s leading integrated marketing communications networks, with more than 7,200 employees globally in more than 54 offices in 46 countries.

For more information, visit us at: www.cheil.com.

We are inviting candidates for the position of:

Content Publishing / Graphic Design Intern (Full-time internship)

Job description

Working with the Samsung Electronics SEA & Oceania business, you will have the privilege of working within a big data environment where strategic decisions are made, guiding best in class upholding brand compliance.

• Content Audit & Analysis: Work closely with the Content Team to conduct content audits on Samsung.com to ensure content is brand compliant and aligns with our strategic objectives.

• Progress Tracking & Reporting: Analyse, track, and report progress on weekly and monthly reports for multi-market operations, providing insights and recommendations for optimization.

• Training Document Management: Prepare and maintain training documents, Standard Operating Procedures (SOPs), and any other necessary documents to support team operations and knowledge transfer.

• Assist in Design Projects: Execute simple design tasks such as key visual adaptations for regional campaigns, ensuring alignment with brand guidelines and creative direction.

• Asset Management: Organize and maintain digital assets, including images, graphics, and other design elements, to facilitate efficient workflow and collaboration within the team.

Desired Skills and Experience

• Good skill in Excel and PPT

• Good skill in Adobe Illustrator and Photoshop

• Pursuing or recently completed a degree in Graphic Design, Visual Communication, or a related field.

• Analytical and quantitative, with strong attention to detail

• Self-starter with excellent communication and collaboration skills, with the ability to work effectively in a team environment.

• Ability to thrive in a fast-paced, ambiguous, interruptive environment

• Ability to work independently as well as work collaboratively toward a common goal

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.
  

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. 2 years of relevant experience in similar field.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

ROLE DESCRIPTION SUMMARY

Join us as a Project Safety Engineer (PSE), where you will be responsible to perform systems safety engineering activities required to develop a safe solution (mainly a software), product or projects. In this role, you will apply your Safety Engineering skills within an interdisciplinary team covering all aspects of a system lifecycle.

KEY ACTIVITIES AND RESPONSIBILITIES

As aProject Safety Engineer, you are accountable for:

As a Project Safety Engineer, you conduct safety engineering activities and produce the required artefacts on time, budget and quality for the allocated project / product.

This includes:

· Conducting a range of activities that identify and address safety hazards and risks by ensuring compliance to legislations, safety policies and the Thales Solution Safety Management System

· Developing and maintaining safety key artefacts: system safety program plans, safety case reports, hazard logs, risk assessments, preliminary system safety assessments and system safety assessments commensurate with the processes, standards and best practices employed by air traffic management domain including fault tree analysis and GSN

· Work closely with the engineering integrated product teams to identify, derive and manage safety requirements, ensure that they are included in the solution design baseline and that their compliance is demonstrated through verification & validation and developing effective mitigations and controls to hazards, procedure and/or training

· Provide timely safety subject matter expertise and engineering support. This includes participating and/or chairing system safety working groups, safety review boards and other safety committees and workshops as required

· Apply Model Based System Engineering tools and modelling methodologies to define system safety functions and requirements as well as managing safety data

· Escalate risks when necessary, provide clear reporting and recommendations

· Work in accordance with Thales processes and practices, and contribute to their improvement

You will also improve the Safety culture within AMS in Singapore by developing, sharing and/or improving safety training material, delivering training as required and pro-active behaviour.

KEY KNOWLEDGE AND EXPERIENCE

To be successful in your role, you will have demonstrated and/or acquired the following knowledge and experience:

SKILLS & ABILITIES

· Experience in the Systems Safety Engineering process in a safety critical industry such a Defence, Land Domain, Manufacturing, Vehicles, Railway, Aerospace, Nuclear or Oil & Gas

· Demonstrated experience applying industry best practice system safety analysis and operational risk management techniques and methodologies

· Proven track record of successfully leading the execution of system safety programs

· Familiarity with Eurocontrol Safety Assessment Methodology and its system safety engineering processes including core system safety analysis techniques: FHA, PHA, PSSA, SSA, ETA, FTA, HAZOP, FMECA, RAM, etc.

· Experience and understanding of the V-cycle and how/when the safety engineering activities are interfaced with

· Knowledge of international standards of the safety domain: ARP 4761/4754, DO-278A/178C, ED-153

· Excellent problem solving and decision-making abilities, great and positive attitude, ability to learn

· Adapt easily to change to work in an agile system engineering environment to understand a problem and provide optimal solution options in terms of size, scale and complexity

· Able to travel to Melbourne, Australia (a few weeks a year).

EXPERIENCE

· Minimum 10 years’ experience in a similar or adjacent role

· Familiar with management and engineering tools such as DOORS, Polarion, JIRA and FTA tool

· Experienced in top-down (abstract ideation) and bottom-up (detailed implementation) approaches in engineering solutions and can work with colleagues with these views

· Knows the structure of a software and be able to apply safety techniques

· Team player: harmonising, influencing, negotiating, seeking feedback and mentoring / coaching

· Self-driven and highly motivated, passionate about systems safety engineering and continual process improvement to achieve optimal outcomes for all stakeholders

· Keen to grow product and process knowledge over time, to enhance your capabilities as a System Safety Engineer within the given environment of practice

· Knowledge of ‘design-to-cost’ approach means and can quickly preform a cost-benefit analysis to different methodologies before executing a system engineering task

· Excellent written and oral communication skills in English

QUALIFICATIONS

· Engineering or Computer Science degree

· System Safety degree

DESIRABLE

· Understand and application of RAMS techniques such as RBD, life data analysis, MTTF, MTBF, MTTR, FMECA

· Knowledge of transverse engineering disciplines: human factor and cyber-security and their links with safety engineering

· Experience in the development of software products and projects in a variety of methodologies, with a particular focus on iterative/agile development

· Conduct independent safety assurance activities including auditing

· Experience in the ATM Domain and related standards (ICAO)

· French language knowledge

General / Special Requirements

· Assist in ensuring a harmonious work environment in all departments that you are working with by upholding Thales' key values.

· An advocate for diversity and inclusion who will be actively involved in implementing change initiatives to achieve our diversity goals

· An advocate for a culture of continuous improvement

· An advocate for Accountability, transparency and curiosity

· Comply with all relevant company Occupational Health, Safety and Environmental policies and framework and work practices with the intent of preventing or minimising accidental exposures to self, colleagues, visitors and/or the environment and to ensure a safe work practises at all times.

· Comply with all relevant Company policies and procedures.

SPECIAL REQUIREMENTS

· Occasional international travel may be required

DesCartes Program (work package 9) is looking for research assistant in UI/UX design and library development. The objective is to develop a user interface and implement libraries as required for the DesCartes Builder, a novel open-source framework for designing, validating, and integrating innovative hybrid AI models and methodologies.

DESCARTES PROGRAM

The DesCartes programme is developing a hybrid AI, combining Learning, Knowledge and Reasoning, which has good properties (need for less resources and data, security, robustness, fairness, respect for privacy, ethics), and demonstrated on industrial applications of the smart city (digital energy, monitoring of structures, air traffic control).

The program brings together 80 permanent researchers (half from France, half from Singapore), with the support of large industrial groups (Thales SG, EDF SG, ESI group, CETIM Matcor, ARIA etc.).

The research will take place mainly in Singapore, at the premises of CNRS@CREATE, with a competitive salary and generous funding for missions.

Read more about the DesCartes program here.

DESCRIPTION

To facilitate the development of the next generation of urban systems, the DesCartes Program is currently developing a software framework that brings together AI components, physics models and data, modelization and control aspects. This framework, the DesCartes Builder, shall play an integral role in developing robust hybrid AI pipelines, as required for the design and deployment of digital twins of urban applications. As a research assistant, you will play a key role in developing the Builder:

• Craft a user-friendly interface:Design an intuitive interface that allows users to define, manipulate and execute the hybrid AI pipelines with flexibility and ease.
• Develop reusable components: Create robust and reusable libraries that will form the foundation of the DesCartes Builder framework.

EXPERIENCE & QUALIFICATIONS

• Minimum Requirements Bachelor or Master in computer science or engineering.
  A first relevant professional experience (master, internships…).
• Required Skills: Rigor, ability to work with autonomy and with a results-oriented mindset.
  Good interpersonal and communication skill; teamwork.
  Knowledge of Python and basics of machine learning
  Basics of UI/UX design
• Preferred Skills: Strong software engineering skills and development methodologies
  Experience with UI/UX design and UI libraries such as Qt,
  Knowledge of C++ & software optimization,
  Experience with Linux development environment (bash, make, etc.),
  Familiarity with machine learning and deep learning libraries (PyTorch, scikit-learn, etc.).
• Keywords: software engineering
  user interface
  library development
  human computer interface
  machine learning
  artificial intelligence

FURTHER INFORMATION & CONTACT

Gross Monthly Salary Range (SGD): 5,500 to 8,000 (depending on suitability and experience).

Workplace address: CREATE Campus, CREATE Tower, 1 Create Way #08-01 Singapore 138602.

Interested applicants, please send your application to:

• Blaise Genest (Prof): [email protected]
• Eduardo de Conto: [email protected]
• DesCartes – Hiring: [email protected]

Please send your application as a single PDF file including CV, cover letter and name/contact (including email addresses) of two referees.

The Bioinformatics Institute (BII), Agency for Science, Technology and Research (A*STR) is seeking applications for an outstanding scientist in the field of quantum computing.

The Bioinformatics Institute (BII) is a computational biology research and postgraduate training institute as well as a national resource centre in bioinformatics within the Biomedical Research Council (BMRC) of A*STAR. Our scientists aim to understand the biomolecular mechanisms that underlie biomedical phenomena by developing sophisticated computational methods to support discovery from a secure and sustainable data hub to cross-disciplinary AI/ML analysis and data integration. We analyse a wide spectrum of biological and clinical data, including omics data (biomolecular sequences, expression profiles, epigenetics data), 3D structures of macromolecules, and biological tissue and macroscopic images from local and international academic, hospital and industry collaborators, public resources and also from in-house efforts. The institute has a vibrant and diverse research portfolio that includes infectious diseases, computational toxicology, precision medicine, oncology and drug discovery.

Job scope and responsibilities:

· Lead efforts in using quantum computing to analyze biomolecular and biomedical data (e.g. protein-ligand interactions, molecular docking, protein/RNA folding, molecular dynamics simulations, imaging, spatial ohmics) and couple it with methods such as quantum machine learning, quantum monte carlo etc, contributing to the development of a broader initiative encompassing AI in drug discovery.

· Collaborate closely with scientists within the Bioinformatics Institute, within A*STAR and within the local ecosystem.

· Lead or participate in research grant proposals.

Requirements:

· Minimum PhD in a related field.

· 2 years or more of postdoctoral experience in quantum computing, demonstrating outstanding research outcomes and strong publication records.

· The candidate must have experience in quantum computing software development/applications, especially with NISQ machines.

· Excellent communication (oral and written) and public speaking skills.

· Strong records of strategic thinking ability.

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.

The Bioinformatics Institute (BII), Agency for Science, Technology and Research (A*STR) is seeking applications for an outstanding scientist in the field of quantum computing.

The Bioinformatics Institute (BII) is a computational biology research and postgraduate training institute as well as a national resource centre in bioinformatics within the Biomedical Research Council (BMRC) of A*STAR. Our scientists aim to understand the biomolecular mechanisms that underlie biomedical phenomena by developing sophisticated computational methods to support discovery from a secure and sustainable data hub to cross-disciplinary AI/ML analysis and data integration. We analyse a wide spectrum of biological and clinical data, including omics data (biomolecular sequences, expression profiles, epigenetics data), 3D structures of macromolecules, and biological tissue and macroscopic images from local and international academic, hospital and industry collaborators, public resources and also from in-house efforts. The institute has a vibrant and diverse research portfolio that includes infectious diseases, computational toxicology, precision medicine, oncology and drug discovery.

Job scope and responsibilities:

· Lead efforts in using quantum computing to analyze biomolecular and biomedical data (e.g. protein-ligand interactions, molecular docking, protein/RNA folding, molecular dynamics simulations, imaging, spatial ohmics) and couple it with methods such as quantum machine learning, quantum monte carlo etc, contributing to the development of a broader initiative encompassing AI in drug discovery.

· Collaborate closely with scientists within the Bioinformatics Institute, within A*STAR and within the local ecosystem.

· Lead or participate in research grant proposals.

Requirements:

· Minimum PhD in a related field.

· 5 years or more of postdoctoral experience in quantum computing, demonstrating outstanding research outcomes and strong publication records.

· The candidate must have experience in quantum computing software development/applications, especially with NISQ machines.

· Excellent communication (oral and written) and public speaking skills.

· Strong records of strategic thinking ability.

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.

UWCSEA Dover has a vacancy for August 2025 for a Teacher of High School and Middle School Design Technology.

The successful candidate must be experienced and passionate about teaching Design and Technology. The role will include teaching both High School and Middle School aged students in curriculum areas such as Product Design, Food Technology, Electronics and Digital Design. At UWCSEA we offer our own bespoke Design Technology and Food Technology courses in Middle School and in Grades 9 and 10. We offer the IB Diploma, Design Technology courses at Higher and Standard Level, in Grades 11 and 12.

The Design Technology Department is composed of a team of enthusiastic and dynamic teachers who work in a very well ­resourced environment for learning. Teaching takes place in dedicated and well resourced Design Technology classrooms and is supported by skilled technicians.

Main Responsibilities

• Teachers should be willing to contribute positively to the collaborative culture of the Design Technology department and broader Middle and High School teams.
• Teachers should construct learning experiences that challenge and inspire students, support the diversity of learners in each classroom and demonstrate a strong commitment to concept-based teaching and learning.
• Teachers should ensure assessments support ongoing learning and provide timely, relevant, and appropriate feedback to students on formative and summative assessments.
• Teachers should demonstrate effective classroom management that shows an understanding of the academic, social, and emotional dimensions of learning.
• Teachers should keep parents informed about the learning of their children, and be proactive in communication with parents.

Expectations and Standards

• Follow the UWCSEA Professional Code of Conduct and Safeguarding Code of Conduct.
• Teach in line with the UWCSEA Teacher Standards

Person Specifications

• A good degree in Design and Technology or a closely related discipline and a recognized teaching qualification or certification are expected.
• Previous experience of teaching Design and Technology in the 11-18 age range is required.
• Teachers should be willing and eager to participate in the five key elements of a UWCSEA education: Academics; Activities; Outdoor Education; Personal and Social Education, and Service.
• Academic expectations include enthusiastic participation in Professional Learning.
• Pastoral expectations include the leadership of a Mentor group.
• On average the College expects a yearly contribution of two sessions per week in each season to Activities and/or Service.
• The College expects that teachers will participate enthusiastically in the curricular Outdoor Education experiences which are relevant to their students and will also occasionally volunteer for holiday Outdoor Education trips.
• A commitment to diversity and inclusion is essential alongside a willingness to adapt and develop pedagogy to meet the needs of our learners.

Applications

The UWC Mission is to make education a force to unite people, nations and culture for peace and a sustainable future. We are committed to creating a community in which all members feel safe and secure, and know that their authentic selves and individual differences are accepted with respect and care. At UWCSEA, we acknowledge that diversity, equity, inclusion and justice (DEIJ) is an ongoing and evolving process and strive to create and sustain a sense of belonging for all members of our community, past, present and future. All qualified applicants, including those who identify as a part of marginalized group(s) and individuals with (dis)abilities are all encouraged to apply. Our school is committed to safeguarding and promoting the welfare of all the students in our care and expects all applicants to share this commitment. We follow safe recruitment practices and all appointments are subject to interview, satisfactory references, identity and criminal record checks.

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

Interested applicants are invited to apply directly at the NUS Career Portal

Your application will be processed only if you apply via NUS Career Portal

We regret that only shortlisted candidates will be notified.

Job Description

• The Research Fellow will work closely with the Principal Investigator, Dr. LIN Yiliang, on the research project of bio-interface design between living systems and materials for healthcare and sustainable applications.
• The Research Fellow will help to develop living materials system integrating functional hydrogels with microorganisms, perform material characterization, and investigate the real-world applications.

Job Requirements

• A PhD degree in a relevant area, e.g., Chemical Engineering, Material Science and Engineering, Chemistry, Biomedical Engineering;
• Good publication record;
• Experienced bio-interface design, construction of living materials, materials characterization, and cell culture.
• Any experience with 1) animal experiments, 2) advanced characterization techniques, and 3) soft matter mechanics and physics, is a plus
• This position is available from Jan 2025

Interested applicants are invited to apply directly at the NUS Career Portal

Your application will be processed only if you apply via NUS Career Portal

We regret that only shortlisted candidates will be notified.

Job Description

To support Finance Lead in the payment workstream, to review and approve payment transactions for the College of Design & Engineering and providing advisory support and ensuring compliance with University’s Financial Policies and Procedures.

Duties & Responsibilities

• Counter-check invoices and Request for Payments (RFP)
• Approve the invoices and RFPs in the system
• Provide advisory on payment policies and procedures
• Other administrative tasks assigned

Qualifications

• O-level or Polytechnic Diploma in any field;
• Preferably with 3-5 years of relevant working experience;
• Meticulous with great attention to details
• A good team player with positive attitude;
• Customer centric mindset and Good communications skill;
• Familiar with MS Office applications;
• Good written and spoken English

GetGo is Singapore’s largest and fastest growing carsharing platform that enables everyone with the freedom to drive, without the burden of ownership. Our vision is to be APAC’s #1 carsharing platform as we seek to create a mobility ecosystem that's shared and sustainable for all.

As a Design Intern, you are a driven and out-of-the-box creative who can help bring to life compelling visual designs that are aligned with our brand narrative, creative concepts and marketing strategies. You will be part of GetGo’s highly energetic and dynamic creative team, collaborating with other creative disciplines to create branded collateral & original campaign content across our platforms such as product, social media, website, editorial, core brand creative initiatives etc.

Our ideal candidate is self-motivated, proactive, has a strong eye for good visual design, and has a strong understanding of digital media and tools to create engaging content.

Day to Day Activities

• Design high quality digital content for our brand platforms such as editorial, internal & external brand communications, quarterly campaigns and core brand initiatives
• Work closely with other creative and marketing peers to conceptualise ideas & translate concepts into exceptional and effective visual directions
• Collaborating with other creative peers with a vision of elevating the work together through craft excellence
• Ability to explore and execute visual directions based on requirements and collaborate with different departments to ensure consistency of designs across deliverables
• Provide creative & design support for photography & film production
• Collaborating with internal departments to establish campaign objectives, complete tasks, and identify and solve problems
• Share knowledge, experience and inspiration on the latest design trends and technology

Who We Are Looking For

• Diploma/Degree in Visual Design / Communication or related studies
• Exceptional sense of brand experience and design
• Strong understanding of design thinking and principles
• A digital native who is curious with a collaborative mindset, you are also a student who is not afraid to experiment and enjoys working with and learning from people
• Organised, motivated and independent conceptual thinker
• You have excellent communication skills and can clearly articulate your ideas
• Flexible and able to adapt working style based on the specific needs of projects
• Good proficiency with visual design tools ie Adobe Creative Suite, Figma
• Proficiency with any motion design tools (ie Adobe Creative Suite, After Effects) is a plus

Why You Should Join Us

• Be part of the fastest growing and largest carsharing technology company in Singapore
• Achieve meaningful objectives as part of a mission-driven and values-based organisation
• An opportunity to experience an open, inclusive, and culture-first work environment

Strong personal alignment with our GetGo Values:

• Driven by Purpose
• Stay Curious and Humble
• Collaborate with Empathy
• Make it Better
• Get It Going!

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Job Description

Do you have a keen eye for design and aesthetics? If you like the chance to create the look and feel of some of our billion dollar brands, this is a role for you!

This creative role is responsible for the design of skincare & beauty retail projects. You will focus on a consumer journey that resonates with the brand's identity and vision while ensuring creative articulation is in line with global strategy and direction.

Your Team

You will report to the Design Director.

Key Responsibilities:

• Retail Design: Responsible for creative design on new concepts and retail formats to elevate consumer journey and brand experience. Oversee and manage projects from brief through design, construction stages and completion and opening for each project. Ensure timely delivery of design, project and opening schedule.
• Project Management: provide support on pilot doors, custom designs and events, and fit-for-use market solutions. Support planning, managing and tracking of project costs and ensure projects meet budget requirements.
• Collaborate: with internal functions including Visual Merchandising team to ensure creative and impactful store presentation. Manage external consultants & vendors/contractors to ensure quality and consistency in the construction of all counter & standalone boutiques across the region.
• Responsible for adapting from Global design guidelines in markets’ roll-out for renovation and new projects in a budget-conscious and timely manner.
• Lead on shop drawing review and validation, factory QC, site reviews and follow up on defect punchlist. Review technical drawing packages and support local markets in cost estimates and value engineering.
• Identify opportunities for cost efficiencies, project savings, and innovative design solutions to enhance overall project delivery.
• Support markets on qualification of new vendors/contractors in support of business needs Train new and existing contractors, providing updates on new techniques, details and directions for store design.

Job Qualifications

• Degree in Interior Design / Architecture or related field
• Minimum 8 years of design experience in architectural/interior or retail store design, with 5 years experience in branded retail or luxury retail environments.
• Strong communication a pre-requisite to manage multiple and diverse markets.
• Ability to influence, communicate and collaborate with different internal functional teams, as well as external teams that include consultants, vendors, contractors and millwork suppliers, to execute completion of projects.
• Ability to understand technical aspects of Retail Design, such as materials and finishes, lighting requirement, furniture design, detailing fixtures, and related fields.
• Extensive network & knowledge of shopfitters, retailers & procurement processes will be highly advantageous to the success of this role.
• Strong analytical skills with an understanding of the Asia retail consumer and market.
• Good proficiency in software programs including AutoCAD and Sketchup.

About us

We produce globally recognized brands and we grow the best business leaders in the industry. With a portfolio of trusted brands as diverse as ours, it is paramount our leaders are able to lead with courage the vast array of brands, categories and functions. We serve consumers around the world with one of the strongest portfolios of trusted, quality, leadership brands, including Always®, Ariel®, Gillette®, Head & Shoulders®, Herbal Essences®, Oral-B®, Pampers®, Pantene®, Tampax® and more. Our community includes operations in approximately 70 countries worldwide.

Visit http://www.pg.com to know more.

Our consumers are diverse and our talents - internally - mirror this diversity to best serve it. That is why we’re committed to building a winning culture based on Inclusion and our ideal candidate is passionate about the same principle: you will join our daily effort of being “in touch” so we craft brands and products to improve the lives of the world’s consumers now and in the future. We want you to inspire us with your unrivaled ideas.

We are committed to providing equal opportunities in employment. We do not discriminate against individuals on the basis of race, color, gender, age, national origin, religion, sexual orientation, gender identity or expression, marital status, citizenship, disability, veteran status, HIV/AIDS status, or any other legally protected factor.

We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

About NSING:

As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products includes General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low Energy BLE and BMS (Battery Management System). When you join NSING, you will be part of a talented team in the Singapore R&D Center where we develop high performance MCU targeting for Industrial and Edge AI applications.

Your Role:

As a SoC Design Verification Engineer, you will be you would be part of a passionate team developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C co-simulation, to mixed-signal simulation and formal verification. You will be part of the Singapore team in developing high performance MCU chips.

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain test benches for complex digital designs using System Verilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Your Skills and Experiences:

• Education：Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 5 years+ prior industry experience of design verification including significant System Verilog and UVM usage.
• Technical skills:

-Deep knowledge of digital logic design, SOC architecture and microarchitecture

- Proficient in simulation-based verification methodologies and languages such as UVM and System Verilog

- Skilled in developing and maintaining test benches, test cases, and verification environments

- Experience across the full verification cycle from initial planning to final tape out

• Preferred skills:

- Knowledge of low-power design techniques and verification methodologies.

- Knowledge of hardware-software co-simulation mixed-signal verification techniques.

- Knowledge of gate level simulation methodologies.

Other Skills:

• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Flexibility and adaptability and demonstrates ability to manage multiple tasks and projects, prioritizing effectively to meet deadlines.

About Us

Our Febreze, Home Care organization is looking for an experienced product design candidate to join our Air Care Membrane platform team, curious to lead the technology development and define Febreze's new S-curve. This is an exciting role for a Product Design Senior Scientist who is passionate about growing the Air Care business.

In this role, you will be a critical team player and partner for Global Febreze team to lead the product design and development of Membrane (Continuous Non Energized) Platform to enable Febreze's vision to cross $2Billion. Together we will define the Febreze's Innovation Master Plan across all consumer jobs to be done.

Your team

Located at the P&G Singapore Innovation Center, you will be part of Air Care Product Design team in Fabric and Home care sector. You will have the opportunity to work with multi-functional teams and engage with both internal and external partners.

Key Responsibilities

• Responsible for introducing fundamentally new technologies, formulations, materials & processes, developing complex technical solutions for meeting consumer propositions.
• Responsible for Technical Project Management, IP strategy, leading Technical readiness assessment, co-creating and influencing the strategic direction of the research work to be done
• Prtnering with other P&G Innovation centers to bring new ideas to life and make a global impact.
• Coaching Researchers and Lab technician of the group in development and delivery of innovation

Qualifications

• Masters degree in Science or Engineering
• 8+ years experience in Product Design/Development and Formulation in FMCG industry
• Able to Lead global programs with excellent cross functional collaboration and project management skills
• Strong technical mastery and a high level of technical and consumer curiosity.
• Ability to build a strong relationship and network both with the R&D and the multifunctional teams.
• Ability to drive analysis and conclusions of technical and consumer work both via written and oral communication.
• High agility and ability to Embrace Change, as midstream work can be both uncertain and shift in priority according to new learning and overall business priorities.
• Leadership and a Passion for Winning by driving projects to success. The candidate should be comfortable with a degree of ownership and independence to lead by example, executing with excellence and using influencing skills to engage both the R&D and the multifunctional team

About us

We produce globally recognized brands and we grow the best business leaders in the industry. With a portfolio of trusted brands as diverse as ours, it is paramount our leaders are able to lead with courage the vast array of brands, categories and functions. We serve consumers around the world with one of the strongest portfolios of trusted, quality, leadership brands, including Always®, Ariel®, Gillette®, Head & Shoulders®, Herbal Essences®, Oral-B®, Pampers®, Pantene®, Tampax® and more. Our community includes operations in approximately 70 countries worldwide.

Visit http://www.pg.com to know more.

Our consumers are diverse and our talents - internally - mirror this diversity to best serve it. That is why we’re committed to building a winning culture based on Inclusion and our ideal candidate is passionate about the same principle: you will join our daily effort of being “in touch” so we craft brands and products to improve the lives of the world’s consumers now and in the future. We want you to inspire us with your unrivaled ideas.

We are committed to providing equal opportunities in employment. We do not discriminate against individuals on the basis of race, color, gender, age, national origin, religion, sexual orientation, gender identity or expression, marital status, citizenship, disability, veteran status, HIV/AIDS status, or any other legally protected factor.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Position Overview:

The Senior/Staff Design Engineer will be responsible for developing micro-architecture for ISP and CV related algorithms, utilizing RTL design using Verilog/System Verilog coding and HLS tools like Catapult. They will analyze metrics such as power, performance, and area to meet key objectives, collaborate with architects and DV Engineersfor efficient verification signoff, and support FPGA tasks such as emulation,validation, and debugging.

Responsibilities:

• Develop micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Analyze and optimize metrics like power, performance, and area.
• Cooperate with verification architects and DV engineers to ensure high quality IP delivery.
• Support backend team for SoC signoff.
• Oversee FPGA tasks including emulation, validation, and debugging.

Qualification/Requirements:

• Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
• Experience: Minimum 5yearsand aboveof experience in ASIC design. Expertise in image signal processing projects is beneficial.
• Technical Skills:
• - Advanced proficiency in HDL languages (Verilog, System Verilog).
• - In-depth knowledge of all phases of ASIC frontend design and sign-off.
• - Extensive experience in image/vision/video data processing or algorithm acceleration.
• - Proficiency in scripting languages like Python, Perl, or C/C++.
• Soft Skills: Excellent leadership, teamwork, and communication skills.
• Additional Notes:Stronganalytical skills and the ability to lead complex projects independently and within teams.

As part of IME Integrated Circuit Design and System Department, we are seeking a candidate with relevant experience in analog integrated circuit design. This candidate will contribute to developing analog circuit blocks e.g. low-power operational amplifiers, voltage/current references, and voltage regulators based on thorough topology analysis. This candidate will work closely with other team members for the circuit design, test verification, as well as system integration and validation for a broad range of innovative sensor systems.

Role & Responsibilities

• Circuit schematic design and simulation, layout supervision, pre-tapeout design verification, test plan development and chip measurement
• Work together with teams to investigate novel circuit/system solutions to create new inventions

Requirements

• Bachelor’s / Master’s degree in Electronic Engineering
• Good understanding of CMOS analog IC design methodologies
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

As part of IME Integrated Circuit Design and System Department, we are seeking a candidate with relevant experience in analog integrated circuit design. This candidate will have the opportunity to develop unconventional ultrasound transducer drivers, receiver circuits for IoT and biomedical applications as well as cutting-edge high-speed analog circuits for advanced optical communication.

Role & Responsibilities

• Design and tapeout circuit blocks e.g. high linearity low-noise amplifier, variable gain amplifier, envelop detector, and high voltage driver for MEMS ultrasound transducers.
• Work together with team on system integration and demonstration.
• Work together with team to investigate novel circuit/system solutions to create new inventions.

Requirements

• Master’s / PhD degree in Electrical Engineering or equivalent
• Minimum 2 years of transistor-level analog circuit design experience
• Good understanding of CMOS analog IC design methodologies and successful tapeout experience
• Familiar with analog IC design and verification flow
• Design experience with high voltage BCD process would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

This is an opportunity to be a key player at a company with a great reputation in IoT semiconductor technology and growing business. We are looking for experienced/senior engineers to join our team in Singapore and be involved to develop the next generation IoT/AI chips based on a revolutionary architecture.

1. Work with team to define the design of WIFI/BT related modules.
2. Develop RTL design of one or more blocks, define RTL module partition, timing requirement etc.
3. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
4. Assist with the development of company documentation and generation of patents.

Qualification

1. Master's degree in Electrical Engineering (or equivalent), with 5+ years’ industry experience.
2. Team player, with good problem solving and communication skills.
3. Proficiency in System Verilog for RTL logic design and verification.
4. Familiarity with the design of digital MAC/baseband/high-speed interface/CPU or DSP is a plus.
5. Experience in Architecture/Block definition for SOC system such as WiFi, Bluetooth and GNSS.
6. Experience in micro-architecture design, and RTL coding with Verilog, familiar with Cadence and Synopsis tools.
7. Experience in synthesis, with analysis of power, timing and area.
8. Review micro-architecture to meet specification requirements and perform Design Quality Check
9. Experience in RTL and gate level simulation, unit test, system test and EDA verification

At Mediatek’s Memory Design Automation team, we work seamlessly with worldwide memory design team to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

Responsibility

1. Responsible for cutting edge technology node’s SRAM compiler design and deliver best quality of design kit.
2. Seamlessly collaborate with SRAM design and layout team to achieve highest quality of design kit delivery.
3. Responsible for data analysis and platform development of memory usage big data.
4. Responsible for physical verification (DRC/ERC/LVS/ANT/PERC) on SRAM compiler.
5. Responsible for spice simulation on timing, power and noise on SRAM compiler.
6. Responsible for QA check and development on SRAM compiler.

Requirements

1. Bachelor or Master Degree in Electrical and Electronic Engineering or Computer Engineering or Computer Science.
2. Multi-task capability and strong self-driven characteristics to meet challenging schedule.
3. Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
4. Strong interpersonal skills to work with team members with multi-cultural environment
5. Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
6. Candidate with experience is preferable.

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Mediatek’s Memory Design Automation team is looking for fresh talent to join us as a modeling engineer for the development of behavioral, FPGA, timing and DFT simulation models. The role will be required to create, debug and optimize SRAM models for ASIC design flow.

The candidate must be a team player, able to communicate clearly and concisely to deliver quality work on time.

About the team:

The Mediatek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness.

What you do:

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.

What you bring:

• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related discipline with at least 3 years of semiconductor industry experience.
• Have at least 3 years experience using Linux systems.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required
• Experience with EDA tools will be helpful:

o DFT: Logicvision, Tessent, Fastscan

o Synthesis: Design compiler, Genus

o Simulation tools:VCS, QuestaSim, NC

o STA tools such as PrimeTime

• Good scripting and flow automation skills, in Perl or Python.
• A team player, meticulous, able to work and learn independently are important attributes for this job.

Location: One North, Singapore