Job Purpose and Key Accountabilities:

As a Management Trainee, your main goal will be to learn and master various aspects of the company's operations, including but not limited to operations management, human resources management, team leadership, decision-making, and problem-solving. Through this training program, you will acquire the necessary skills and knowledge to prepare for future senior management positions.

Key Accountabilities:

1. Continuously learn and understand the specific business operations and management strategies of the company.
2. Participate in and lead team projects, enhancing teamwork and leadership.
3. Effectively manage and execute projects in a multitasking and high-pressure environment, with a results-oriented approach.
4. Solve problems encountered in work, formulate and implement solutions, emphasizing replicable processes.
5. Embrace change, continuously improve your skills and knowledge, and break through your own capability boundaries.

Main Duties and Responsibilities:

• Participate in the company's daily operations and management activities, learning the company's business processes and strategies.
• Assume a leadership role in projects, effectively distribute tasks and manage progress, ensuring smooth completion of projects.
• Think independently when encountering problems, propose and implement solutions, and conduct a review after problem resolution.
• Accept feedback from superiors and colleagues, continuously improve your skills and knowledge, and maintain positive energy with an open mindset to change.
• Enhance your professional knowledge and skills by participating in the company's training and learning activities and continuously learning.

Job Specification:

• Education: Fresh graduates from NUS/NTU/SMU in Singapore or those with one to two years of work experience. Bachelor's or master's degree in business management, education, psychology, or other related fields.
• Skills: Leadership and teamwork abilities, problem-solving and decision-making capabilities, project management skills.
• Personal Characteristics: High self-drive, leadership, adaptability, resilience.
• Career Goals: Passionate about education and training, looking forward to long-term development in the company, willing to take up a management position after completing the training.
• Others: Deep understanding of the education and training market in Singapore, familiar with basic information technology and software applications.

Working Hours (43 hours per work week):

Mon : off

Tuesday - Friday : 1.30pm - 7.30pm

Saturday and Sunday: 9.00am - 7.30pm

Responsibilities:

• Manage and support the interior design development and coordination process throughout the design and documentation phases.
• Manage the execution of interior works from tender till completion and handover
• Monitor to ensure resolution of design and technical coordination issues at site
• Review of Contractors’ submissions, work schedules, materials samples, shop drawings etc.
• Conduct site & factory visits, monitoring of quality of on and off-site fabrication
• Monitor and report of interior works progress and qualities, to ensure delivery timeline and workmanship

Requirements:

• Degree in Interior Architecture / Architecture or any related field
• At least 6 years of relevant experience in Interior Design & Site Execution, preferably with premium residential, offices, hotels experiences
• Self-driven, and able to work independently.
• Ability to multi-task and to work under pressure.
• Excellent problem-solving skill.
• Strong organizational, communication and interpersonal skill.
• Proficient in Project Management Programs, AutoCAD, SketchUp, 3D Max, Illustrator or other design programs, Microsoft Excel, Word, etc.

Meet the Team

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

Responsibilities

The chosen candidate will contribute to, and manage a team for, the development of architecture, microarchitecture, and design of complex, low power, Wireless SoCs. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML, while meeting best-in-class power and performance targets. The Chip Design lead will define architectures with embedded multi-core, multi-threaded processor subsystems, AI accelerators, bus interconnect, memory architecture and multi-level caches to satisfy performance and throughput requirements. This will include RISC-V, ARM or proprietary processor designs, high-speed interfaces for off-chip memories, integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process.

• Lead the development and execution of Wireless SoC’s from definition, through execution, and into production
• Definition and Planning
  Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates.
  Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse.
  Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies.
• Project Execution
  Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation.
  Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure.
  Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams.
  Follow established quality procedures and processes to achieve first tapeout.
• Validation to Production
  Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification.
  Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary

Skills You Will Need

Minimum Qualifications:

• B.Tech/M.Tech in related branches of electronics and computer science with a minimum of 10 years of related experience.
• Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus.
• Top-down planning and execution of SOC projects.
• Experience in full-chip development cycle
• Able to build strong technical team.
• Hands-on experience in architecture, micro-architecture, digital design processes
• Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
• Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
• Knowledge of processors like RISC-V and ARM processors
• Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
• Knowledge of DFT including Scan, ATPG, MBIST
• Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
• Knowledge of hardware accelerators
• Knowledge of Verilog and System Verilog
• Knowledge of scripting languages like Perl, Python, Tcl, shell

Benefits & Perks:

You can look forward to the following benefits:

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station

About the Team

The Digital Subsystems team is responsible for the research and development of digital architectures and IPs from concept to production. We develop compute engines (AI/ML), processors (RISC-V), accelerators, peripherals and system IP. Our activities include advanced research & development, high-level modeling, architecture, RTL design, timing/power/area optimization, formal and UVM verification within an automated framework. We value innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team.

What we’re looking for:
The Verification Lead will be responsible for technical leadership, direction-setting and significant hands-on contribution of advanced digital verification projects. The lead will have direct responsibility for the planning and execution of methodology and flows to be employed in the execution of verification projects. The lead will directly supervise the technical activities of verification projects such as test planning, execution, and reviews at both IP and system-levels. Included is communicating and synchronizing methodology and test development with verification leads and engineers at other sites. The lead is also expected to provide technical coaching and mentoring to team members on verification approaches, languages, and tools/methodologies.

Skills you’ll need:

• Provide technical leadership for a team of verification engineers
• Generate and execute verification plan based on specifications
• Architect and implement testbenches using UVM-based constrained-random
• Utilize architectural models to verify functionality of digital IP
• Develop integration and reuse guidelines for IP integration
• Coverage definition, implementation, and analysis
• Mentor junior engineers
• Support IC teams in integration and use of IPs
• Develop and improve flows and methodologies for efficient and high-quality development
• Skill development and training on modern verification techniques such as formal

Required Experience & Skills:

• Technical Team leadership and project execution ownership
  Ability to plan, track and manage a complex verification project comprising of a team of engineers
  Ability to mitigate unforeseen obstacles and maintain on-time execution to meet project schedules
  Technical leadership and mentorship
• Extensive experience with implementation of UVM testbenches:
  Verification component design with emphasis on decoupled stimulus and checking, robust random stimulus generation and reuse
  Reuse of IP-level testbenches in subsystem and system-level verification
  Assertion-based verification
• Ability to define and specify requirements for verification-related flows including:
  Simulation control and coverage
  Regression deployment and coverage collection
• Experience with EDA simulation tools

Preferred Experience & Skills (any of the below):

• Experience in deploying and maintaining formal verification applications for system-level connectivity verification.
• Experience in deploying and maintain formal property verification at an IP-level for interface protocol and internal functional verification.
• Experience in developing and deploying executable and reusable test plans and tracking their closure through regression
• Experience in verification of microprocessors
  Developing and debugging assertions with formal property verification for interface verification and/or internal processor operation
  Experience with processor debug techniques and design including test interfaces, debug and trace implementation and general debug infrastructure
  Experience developing and maintaining software toolchain and infrastructure to facilitate software testing of processor implementations.

​

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 8 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel

o Emphasize system-level perspective in the design process, considering overall system architecture and functionality

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments

o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 5 years of ASIC design experience preferred.
• Familiar with ASIC design flow
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting
• A team player with good communication skills
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 8 years of ASIC design experience preferred.
• Familiar with ASIC design flow
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting
• A team player with good communication skills
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 3 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

We are looking for a candidate for high-speed analog and mixed-signal integrated circuit design. This candidate will contribute to the development of high-speed silicon photonics transceiver for next generation wireline communication system. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications.
• Design and tapeout ICs which include state-of-the-art circuit blocks e.g. analog-to-digital converter, equalizers (CTLE, DFE) as part of the high-speed data link system.
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electrical Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog and mixed-signal IC design methodologies and successful tapeout experience
• Familiar with analog and mixed-signal IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

We are looking for a candidate for high-speed analog and mixed-signal integrated circuit design. This candidate will contribute to the development of high-speed silicon photonics transceiver for next generation wireline communication system. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications.
• Design and tapeout ICs which include state-of-the-art circuit blocks e.g. analog-to-digital converter, equalizers (CTLE, DFE) as part of the high-speed data link system.
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electrical Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog and mixed-signal IC design methodologies and successful tapeout experience
• Familiar with analog and mixed-signal IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel

o Emphasize system-level perspective in the design process, considering overall system architecture and functionality

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments

o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 3 years of ASIC design.
• experience preferred.
• Familiar with ASIC design flow.
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving.

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-Level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 5 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler), Photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

We are looking for a candidate for high-speed analog integrated circuit design. This candidate will contribute to the development of high linearity silicon photonics modulators for 6G and beyond communication systems. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications
• Design and tapeout ICs which include state-of-the-art circuit blocks, e.g. wideband linear low-noise amplifier and transimpedance amplifier with a focus on circuits interfacing with silicon photonics elements
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electronic Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog IC design methodologies and successful tapeout experience
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

Responsibilities:

• Collaborate closely with the Project Director and multidisciplinary teams to develop innovative design solutions, from concept through to construction.
• Manage project and design processes, ensuring timely delivery and adherence to deadlines, budgets, and regulatory requirements.
• Supervise and review drawings to ensure design constructability, contributing to firm-wide design excellence and problem-solving.
• Demonstrate creative thinking abilities and contributes to firm-wide design excellence and problem solving.
• Provide influencing ideas to enhance team productivity.
• Collaborate with project managers to execute design visions within project constraints, including timelines, budgets, and regulatory requirements.
• Ensure project filing is accordance to officewide standard system.
• Incorporates integrated sustainable design solutions into projects.
• Participates in managing client relationships and representing Company Brand when meeting with clients and other consultants.
• Attend presentations and meetings with client, consultants, and key stakeholders.
• Understands company agreements, contracts, and deliverables, and assures that company standards for project management are met.
• Contribute to the firm's promotion by participating in professional organizations and events, including international travel for project meetings, site visits, and business development as necessary.

Requirements:

• Bachelor's or Master's degree in Landscape Architecture, Architecture, or related field from an accredited institution.
• 7 to 10 years of professional experience in landscape architecture or related design field, demonstrating creative excellence.
• Proficient in AutoCAD, Revit, Adobe Creative Suite, SketchUp, Rhino; familiarity with BIM (Building Information Modeling) is a significant asset.
• Exceptional verbal and written communication skills, able to present concepts clearly and persuasively.
• Strong teamwork and interpersonal abilities, with experience in multidisciplinary collaboration.
• Professional licensure preferred but not required.

Job purpose:

Assist in the maintenance of accounting principles, practices, and procedures to ensure accurate and timely financial statements

Job description:

• Handle full set of Account (AP/AR/GL) using Odoo.
• Prepare monthly financial Statements, management reports and other reports for fixed Asset, Stocks, Bank, Schedules etc.
• Handle day-to-day accounts activities.
• Handle any ad-assignments assigned by Director and Accountant

Requirement:

• Minimum Diploma in Accountancy
• 2 years’ relevant working experience in preparing full sets of accounts preferred

Muzart Beauty World Centre is looking for a Part Time art Teacher. The candidate should have a portfolio (personal/school) as well as enjoy engaging and connecting with children aged 4-10 years old. She should have a cheerful personality and must be able to speak and update parents well after class.

Curriculum and training will be provided.

Classes are 1.5h each and we will try to provide back-to-back classes to make your time worthwhile.

Requirements

- Weekend availability a must

- Some Weekday afternoons (optional)

- Art Students/Graduates from Art schools welcome

- Passionate art lovers without formal art education may also apply if portfolio meets requirements

Salary: $12/h

WhatsApp 96855952 with CV & portfolio.

Interested applicants are invited to apply directly at the NUS Career Portal.

Your application will be processed only if you apply via NUS Career Portal.

We regret that only shortlisted candidates will be notified.

Job Description

• The candidate is responsible for the design of highspeed wireline transmitter >100Gbps.
• The candidate needs to work on the system architecture, schematic design, and mask layout.
• He/she also needs to perform pre and post-layout simulation to ensure the functionality and performance.

Qualifications

• Bachelor or Master degree in Electrical Engineering.
• Experience in EDA tools usage, including Cadence, Spectre, EMX, Synopsys, as well as Matlab.
• Some knowledge on communication system, such as BER, eye diagram, modulation/demodulation, pre-emphasis and etc.
• Open to Fixed Term Contract.

Interested applicants are invited to apply directly at the NUS Career Portal.

Your application will be processed only if you apply via NUS Career Portal.

We regret that only shortlisted candidates will be notified.

Job Description

• The candidate is responsible for the design of highspeed wireline receiver >100Gbps.
• The candidate needs to work on the system architecture, schematic design, and mask layout.
• He/she also needs to perform pre and post-layout simulation to ensure the functionality and performance.

Qualifications

• Bachelor or Master degree in Electrical Engineering.
• Experience in EDA tools usage, including Cadence, Spectre, EMX, Synopsys, as well as Matlab.
• Some knowledge on communication system, such as BER, eye diagram, modulation/demodulation, pre-emphasis and etc.
• Open to Fixed Term Contract.

We are hiring Junior/Senior Interior Designers !

Drop us an email with your resume today!

Email: [email protected]

Responsibilities:

• understand homeowner requirement and propose space planning with layout and material
• draw in 2D AutoCAD & 3D Sketch Up
• responsible to work out quotation
• responsible to supervise work progress and meet the timeline
• responsible to liaise with suppliers and subcontractors in order to have good quality works

Requirements:

• O level(Min), Diploma, Degree/Bachelor
• Min 1 years’ experience in interior design or construction project management or related experience
• Strong problem solving and analytical skills
• Able to converse in English and Mandarin(in order to handle queries and concerns from English and Chinese speaking counterparts in regards with the interior design related matters.)
• Creative, independent, self-discipline, willing to learn, love to talk to customer and meticulous
• Good communication and like to do presentation, able to meet client at weekend and public holidays

Why join us?

• SIDA Best Design Award Winner
• Qanvast Top 3 Interior Design Firm
• SuperTrust Award Winner Interior Design Firm
• Well-Known Boutique Interior Design Firm
• New 3500sf Design Show Room
• Plenty of opportunities to grow as a pioneer in our company
• Salary based or Profit sharing based

Key Responsibilities:

• The design verification engineer is expected to check, test, and gate the product design for both performance and reliability.
• Draft a test plan to cover each feature in product spec, certification requirement, and customer application.
• Support on DFMEA documentation draft and maintenance.
• Test products' electrical & mechanical performance and reliability with lab equipment such as multi-meter, integrating sphere, oscilloscope, and environmental chamber.
• Testing equipment management & maintenance.
• Follow up on the quality issues found and verify the effectiveness of corrective action.
• Give quality input during the early design stage to avoid potential quality issues.
• Update & deliver the test reports to the project lead and define the quality level of R&D stages.
• Work with QA to ensure the design quality can be delivered to the next phase.

Requirements:

• Bachelor’s in Electronic Engineering, computer science, or relevant majors.
• At least 8 years of design, testing, or quality experience.
• Experience in power electronics product testing and understanding of electronic product schematics is required.
• Operation experience with basic electronic equipment like oscilloscope, multimeter, power supply, and load are required.
• Knowledge or experience in electronic design, design quality, MCU, FW testing & appliances is preferred.
• Able to travel overseas.
• Familiar with UL standards will be an added advantage.
• Proficient in English and chinese to liase with HQ counterpart

1. Perform piping design and pipe support design.

2. Interpret and develop PFD & P&ID.

3. Apply international standard and practices such as ASME, ANSI code. Familiar with pipe / tank specifications, nozzle specifications and orientation of nozzles.

4. Perform Material Take Off (MTO) from piping drawings.

5. Perform pipe stress analysis and surge analysis.

6. Responsible for reviewing of piping/mechanical documents and specification from clients and consultants.

7. Responsible for review and check of all piping/mechanical documents and drawings from vendors and suppliers.

8. Prepare technical datasheet and specification.

9. Co-ordinate with engineers of either disciplines within the department.

10. Liaise with clients, consultants, sub-contractors to resolve technical issue at site or in office.

11. Lead and interface within inter-disciplines for all technical matters.

12. Pre-procurement preparation including evaluation of technical and commercial bid from vendor and supplier.

13. To provide engineering support in tendering of new project such as preliminary design, material and cost estimates etc.

14. Provide technical support to project team for on-going projects and resolve any technical issue on site.ue on site.

• To carry out electrIcal related detailed design and preparation of drawing
• To interpret and develop P&ID, technical data sheet preparation and I/O wiring diagram
• To carry out electrical calculation for the design
• Responsible for reviewing of electrical documents and specification from clients and consultants
• To check and review all electrical related drawings and documents from suppliers and vendors
• To liaise with clients, consultants, sub-contractors to resolve technical issue at site and in office
• To co-ordinate with engineers of other disciplines within the department
• To prepare Pre-procurement including evaluation of technical and commercial bid from vendor and supplier
• To provide engineering support in tendering of new projects such as preliminary design, material and cost esimates etc
• To provide technical support to project team for on-going projects and resolve any technical issue on site
• To assist in preparation of project schedule, related work procedure/method of statement and monthly progress claim

Key Responsibilities:

• The design verification engineer is expected to check, test, and gate the product design for both performance and reliability.
• Draft a test plan to cover each feature in product spec, certification requirement, and customer application.
• Support on DFMEA documentation draft and maintenance.
• Test products' electrical & mechanical performance and reliability with lab equipment such as multi-meter, integrating sphere, oscilloscope, and environmental chamber.
• Testing equipment management & maintenance.
• Follow up on the quality issues found and verify the effectiveness of corrective action.
• Give quality input during the early design stage to avoid potential quality issues.
• Update & deliver the test reports to the project lead and define the quality level of R&D stages.
• Work with QA to ensure the design quality can be delivered to the next phase.

Requirements:

• Bachelor’s in Electronic Engineering, computer science, or relevant majors.
• At least 5 years of design, testing, or quality experience.
• Experience in power electronics product testing and understanding of electronic product schematics is required.
• Operation experience with basic electronic equipment like oscilloscope, multimeter, power supply, and load are required.
• Knowledge or experience in electronic design, design quality, MCU, FW testing & appliances is preferred.
• Able to travel overseas.
• Familiar with UL standards will be an added advantage.
• Proficient in English and chinese to liase with HQ counterparts.