Requirements & Responsibilities
- Expert in RTL Coding/Integration and Synthesis
- Engage in design and micro-architecture development phases
- Participate in macro defining specification, testing and verification of the IP components.
- Perform RTL-level design, including micro-architectural, of the digital portions of the IP architecture
- Work closely with methodology, PD teams to implement RTL design into GDSII.
- Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks
- Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
- Good understanding and working knowledge in other domains like DV and DFT, timing closure
- Able to provide timing constraints and work with PD teams to ensure RTL meets timing
- Strong debugging and scripting skills (Perl, Python, TCL)
- Ability to work with DFT teams to improve test coverage
