Job Responsibilities
1. Responsible for DDR/LPDDR/HBM and other storage/memory interface PHY IP competitive analysis, roadmap planning and specification formulation;
2. Responsible for the design and implementation of PHY IP architecture for storage/memory interfaces such as DDR/LPDDR/HBM;
3. Responsible for the development and delivery of inhouse-developed storage/memory interface PHY IP and achieving corresponding PPA indicators;
4. Assist the back-end team to complete the physical implementation of PHY IP and timing closure;
5. Responsible for the design and implementation of test pieces, packaging design, test board design, post-silicon bring up and testing related work.
Job Requirements
1. More than 10 years of experience in DDR/LPDDR/HBM PHY IP design and successful tape-out;
2. More than 5 years of experience in DDR/LPDDR/HBM PHY IP architecture design;
3. Successful development experience of advanced technology DDR5/LPDDR5/5X/HBM3 PHY IPs;
4. Familiar with the DDR/LPDDR/HBM and other storage/memory interface PHY IP market and competitive landscape, and has rich experience in product road mapping and product definition;
5. Those who are familiar with JEDEC DDR/LPDDR, ONFI/HBM/GDDR and other related protocols will be given priority;
6. Candidates with experience in DDR/LPDDR/HBM and other subsystem development, tape-out, debugging and successful mass production will be given priority;
7. Have good communication skills, high sense of responsibility, strong sense of delivery, and excellent team spirit.
