- Responsible for microarchitecture design and RTL code implementation of internal modules for RISC-V architecture CPU cores.
- Assist verification engineers with unit-level simulation verification, coverage analysis, FPGA verification, and chip debugging for the modules.
- Collaborate with the back-end team on chip-level verification, physical implementation, and performance analysis.
- Participate in chip architecture design and specification definition.
- Responsible for writing design documentation.
Requirements:
- Bachelor's degree or higher in Computer Science, Electrical Engineering, or related fields.
- Proficient in hardware description languages such as Verilog.
- Familiar with chip design and verification processes.
- Experience in developing high-performance CPU processors (ARM, x86, RISC-V, MIPS) is preferred.
- Experience in designing at least one of the following modules (L1/L2 Cache, MMU, Load/Store, Branch Prediction, Vector Extension) is preferred.
- Excellent learning ability, strong communication and collaboration skills, and a diligent and inquisitive work ethic.
DISCLAIMER
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.
Enna Chong
EA 12C6130/ R22109962
