Design Verification Engineer
(Singapore location)
Job Descriptions
Skills:
Skilled in Verilog, System Verilog, UVM
Experience IP Level & SOC Level Verification.
High Experience in defining block, Sub-System and SOC top level test plans.
Experienced with System Verilog assertions, code and functional coverage implementation and analysis.
Experience with one or more high speed protocols is an added advantage.
Requirements
Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 5 year of experience
Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
Strong understanding of verification process from test plan to coverage completion
Strong communication and Analytical skills
Understanding of HDL (Verilog, VHDL)
Experience with designing with FPGA using Vivado is a plus
Interested applicants, kindly send in a copy of your resume stating your current and expected remuneration together with the notice period.
