Responsibilities:
- Design and Implementation: review purchased IP data, deliverable schedule, tool flows, licenses, and PDK with cross-function teams
- Floor planning and Place-and-Route: Utilize Cadence Digital Implementation tools for floor planning, placement, CTS, and routing. Optimize power, performance, and area (PPA) metrics.
- Clock Tree Synthesis (CTS): Create efficient clock distribution networks to meet timing requirements.
- Static Timing Analysis (STA): Perform STA to ensure timing closure and meet design specifications.
- Physical Verification: Work on DRC (Design Rule Check) and LVS (Layout vs. Schematic) checks to ensure design manufacturability.
- Collaboration: Collaborate with cross-functional teams, including front-end designers, verification engineers, and packaging experts, to ensure seamless integration.
- Low-Power Design: Implement low-power techniques such as clock gating, power gating, and voltage scaling as a plus.
Requirements:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Knowledge of Foreplaning, CTS, Power, and static timing analysis.
- Understanding of low-power design methodologies.
- Scripting skills (Linux, Shell, Tcl, jobs scheduling) for automation.
- Ability to address design challenges and have ambitions to resolve new tool and flow issues.
Interested candidates who wish to apply for the advertised position, please click APPLY to submit your resume.
EA License No.: 13C6305
Reg No: R1770654
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