About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
We are looking for an analog custom layout engineer to contribute to the development of High-Speed Connectivity, Broadband Analog and Computing/Storage-Memory Data-Transport products (including functional blocks such as high-speed digital, multi-GHz ADC/DAC, PLL/DLL serial and parallel I/O, and clock generation/distribution for custom ICs). The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, managed a custom analog layout team, successfully performed top-level integrations, and placed products into volume production multiple times.
What You Can Expect
- Experienced in Cadence “Virtuoso VXL” and/or Synopsys “Custom Compiler” layout tools
- Experienced in Mentor Graphics “Calibre” drc/lvs verification tool
- Good problem-solving skills
- Strong communication and presentation skills
- Ability to lead a chip/macro with leading a team, including remote design teams
- Ability to work across functions and levels
- Fluent in English
What We're Looking For
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience.
- Master’s degree in Computer Science, Electrical Engineering or related fields with 5+ professional experience.
- Deep understanding of layout methodology from initial chip planning to tape-out.
- Experiences in advanced process technology and FinFET is preferable.
- Should have a high level of proficiency at LVS, DRC debugging.
- Should have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Should have a high level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
- Strong technical and analytical background, problem solving skills, etc.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
To apply, kindly submit your application via this link:
https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Singapore/Senior-Engineer--Analog-Layout_2401096
