Responsibilities:
- Verification planning. Drive review of verification plan with design and concept engineering.
- Implementation or adaptation of SoC test cases according to plan.
- RTL & gate-level simulation / signoff including functional and code coverage closure
- Test suite quality assurance using e.g. Certitude tools.
- Debug of test failures in RTL & gate-level simulations.
- Issue/bug tracking including driving for closure with concept and design engineering.
- RTL design using the Very High-Speed Integrated Circuit Hardware Description Language (“VHDL”).
Requirements:
- Bachelors or Masters in Electrical/Electronic Engineering
- At least 5 years of experience in related industry.
- Python programming background is required as well.
- Background in Formal Verification and Formal Equivalence Check is required.
- Prior Knowledge: SOC Verification, Formal Verification
