Responsibilities:
- Relevant work experience in physical design implementation of large ASICs (100 to 400 million gates complexity).
- Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
- In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
- Utilize commercial and in-house EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
Requirements:
- Familiarity with one or more VLSI design tools for Place&Route, verilog simulation, DRC/LVS verification, timing analysis, scripting languages.
- Proficiency in UNIX/Linux is advantageous.
