What you will do
- Responsible for standard cell test key design of leading-edge process node (4nm/3nm/2nm), from schematic netlist to gds.
- Work with layout engineer for test key implementation and physical verification including DRC/LVS/ERC/ANT.
- Perform layout extraction, simulation, testing data collection and processing.
- Analyze simulation and silicon data including performance, power correlation, big data analysis, AI model training.
- Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
- Develop advanced library generation methodology and flow, including timing & power characterization, kit generation, regression, and quality assurance, involved with data analysis and machine learning as well.
What you bring
- BS/MS in Electrical and Electronic Engineering/Computer Engineering/Computer Science with minimum 3 years(MS) or 5 years(BS) industry experience.
- Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
- Experience of test chip design in FinFet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
- Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
- Strong communication and teamwork skills to collaborate effectively with cross-functional teams.
Location: One North, Singapore
