Total 3 quality control engineer job vacancies in Art / Design / Entertainment category in Singapore

As a Package Design Engineer within the Package Development and Engineering (PDE) organization in Micron Technology, you will provide package definition and designs for advanced semiconductor devices. You will be working with a multi-functional team across several geographies to create package design databases such as package stack-up, simulation, route-study, substrate/lead frame layout, wire bond diagrams, and other design documentation. You will be ensure the completion of design activities within the project schedule and ensure that design outputs are within Assembly and vendor capability.

Responsibilities will include, but are not limited to:

• Conduct feasibility studies for various package options and assess designs for manufacturability and reliability.
• Work closely with multi-functional team to address packaging design challenge in the area of layout, electrical, thermal, mechanical, assembly and reliability.
• Interact with PDE assembly team and external assembly subcontractor partners to recommend package solutions to meet customer and/or market requirements
• Generate and update assembly documents in database. Provide drafting and drawing support for package drawings, interposer drawings, and manufacturing drawings.
• Support package and DFMEA reviews with assembly engineering and subcon teams.
• Support package technology development, including material selection, process development, DOEs, and related activities
• Support package technology development, including material selection, process development, DOEs (Design of Experiments), and related activities.
• Track and drive program milestones to ensure timely development execution.
• Provide design support for thermal/mechanical/electrical simulation analysis.
• Support and contribute to the Global Design, Simulation and Substrate (GDSS) team on continuous improvement efforts such as:Global design alignment activities
  Continuous improvement efforts
  Package design rules
  Package roadmaps
  Competitive Analysis review

Requirements:

• Master (preferred) or Bachelor of Science degree in Electrical Engineering or Mechanical Engineering with a minimum of 5 years of experience in semiconductor packaging industry OR PhD graduates in Electrical Engineering
• Candidates must possess a strong design knowledge of high-density (Wirebond + Flip-Chip) packaging architectures, die stack-up, packaging layout optimization.
• Excellent communication skills, both oral and written in English.
• Excellent problem solving and analytic skills.
• Experience with Cadence SIP, APD and AutoCAD software tools is preferred.
• Good understanding of Silicon IP, floorplan and Signal/Power Integrity is a plus.
• Ability to work independently, prioritize and manage numerous projects with minimum supervision.
• A global perspective and the ability to work in a multicultural environment.

Performs semiconductor design engineering assignments including engineering and designing packaging stack-up, layout checking, documenting specifications, modifying and evaluating packaging risk in the areas of electrical, thermal, mechanical and reliability. Reviews package design requirements, define the package stack-up and conduct final design review. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor Packaging.

• Responsible the package design integration activities by working with cross-functional team and partners for package technology development, including material development, process development, DOEs, and related activities.
• Work with a cross-functional team across several geographies to create package design databases such as package stack-up, wire-bond fanout, route-study, substrate layout, wire bond/Die placement diagrams, and other design documentation.
• Work with Business Unit Package Design Lead and cross-functional team to establish a Packaging Roadmap.
• Contribute to package design rules and system development.
• Participate in packaging IP development activates and industry benchmarking.
• Work with Substrate and PCB (Printed Circuit Board) suppliers, OSATs (Outsourced Semiconductor Assembly and Test), and other ecosystem partners to meet their requirements with packaging solutions.

Requirements:

• Bachelor of Science degree in Electrical Engineering or Mechanical Engineering with a minimum of 7 years of experience in semiconductor packaging industry.
• Candidates must possess a strong design knowledge of high-density (Wirebond + Flip-Chip) packaging architectures and die stack-up.
• Excellent communication skills, both oral and written in English.
• Excellent problem solving and analytic skills.
• Experience with Cadence SIP, APD and AutoCAD software tools is preferred.
• Good understanding of Silicon IP, floorplan and Signal/Power Integrity is a plus.
• Ability to work independently, prioritize and manage numerous projects with minimum supervision.
• A global perspective and the ability to work in a multicultural environment.

As a NAND Silicon Design Validation Senior/Principal Product Engineer at Micron Technology, Inc., you will be responsible in developing, validating, characterizing, and qualifying new state-of-the-art NAND Flash memory products. In this role, you will be involved in pre-silicon conceptual design and preparation work, run simulations, create and maintain design and validation documentation, analyze bench and parametric data as well as to debug & resolve yield, quality and reliability failures due to design related issues. You will also refine and develop best known methods and automation for design validation of current and future products.

You will also be responsible to work with NAND R&D, Designers and other various Engineering functional groups to troubleshoot, develop and validate new designs to meet specific product requirements. Product Engineers are the key product-specific point of contact for critical issues and act as the main interface between Research and Development, Manufacturing, Business Units, and Quality Assurance departments.

Responsibilities:

• Responsible for new product startup to deliver product specifications and requirements
• Define and validate product configuration parameters
• Create validation flow for silicon design margin characterization and validation in volume.
• Support design verification and in-depth circuit of new products using CAD tools and Verilog simulations
• Identify design marginalities and recommend design fix for circuit-related problems
• Perform electrical failure analysis to understand the root cause of device marginalities or failures
• Utilize engineering bench and testers to perform device characterization and electrical failure analysis

Qualifications/requirements:

• At least bachelor degree from electrical/electronicsor Computing engineering.