Total 9 staff nurse job vacancies in Art / Design / Entertainment category in D18 Tampines, Pasir Ris

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

• We are a chip design service company invested by an international consortium and founded by a senior chip design technical team.
• The company is headquartered in Singapore and will take root in Singapore for long-term development.
• The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.
• We have rich industry experience and deep practical accumulation in ASIC design and business management.

Our office is located in one North and walking distance from MRT.

We Provide competitive salary and compensation package for the right candidate. We are work-life balance and friendly to employees with various benefit.

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered. ( for excellect junior candidates with 3+ years experience will be considerated )

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

What you will do

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek:

• Scan chain insertion & ATPG pattern generation
• Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
• Diagnosis to help manufacture process improvement

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:

• PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
• Develop & integrate DFT-related RTL design modules to test chip

What you will bring

1. Master's Degree in EEE/ EE/ CE
2. Expertise in Synopsys and/or Mentor DFT tools, and HDL simulators like Synopsys VCS
3. Fluency in script language including but not limited to TCL/Perl/Python
4. Experience about MBIST with state-of-the-art SRAM structure & EDA tools is big plus
5. Skill for RTL design & integration, and physical failure analysis(PFA) will also be plus
6. Ability to think and work independently with different teams
7. Interest in understanding more details in entire design flow
8. Ability to use English for discussing technical details
9. With a minimum of 7 years relevant industrial work experience

About the company

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact.

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

Position Overview:

The Senior/Staff Design Engineer will be responsible for developing micro-architecture for ISP and CV related algorithms, utilizing RTL design using Verilog/System Verilog coding and HLS tools like Catapult. They will analyze metrics such as power, performance, and area to meet key objectives, collaborate with architects and DV Engineersfor efficient verification signoff, and support FPGA tasks such as emulation,validation, and debugging.

Responsibilities:

• Develop micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Analyze and optimize metrics like power, performance, and area.
• Cooperate with verification architects and DV engineers to ensure high quality IP delivery.
• Support backend team for SoC signoff.
• Oversee FPGA tasks including emulation, validation, and debugging.

Qualification/Requirements:

• Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
• Experience: Minimum 5yearsand aboveof experience in ASIC design. Expertise in image signal processing projects is beneficial.
• Technical Skills:
• - Advanced proficiency in HDL languages (Verilog, System Verilog).
• - In-depth knowledge of all phases of ASIC frontend design and sign-off.
• - Extensive experience in image/vision/video data processing or algorithm acceleration.
• - Proficiency in scripting languages like Python, Perl, or C/C++.
• Soft Skills: Excellent leadership, teamwork, and communication skills.
• Additional Notes:Stronganalytical skills and the ability to lead complex projects independently and within teams.

• We are a chip design service company invested by an international consortium and founded by a senior chip design technical team.
• The company is headquartered in Singapore and will take root in Singapore for long-term development.
• In the future, we will also open branches in China, Japan and other places. The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.
• We have rich industry experience and deep practical accumulation in ASIC design and business management.

Our office is located in one North and walking distance from MRT.

We Provide competitive salary and compensation package for the right candidate.

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered. ( for excellect junior candidates with 3+ years experience will be considerated )

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

Position: Enrolled/Staff Nurse (Toa Payoh/Thomson) | Up to $5500 | 5.5 Days

Location: Toa Payoh / Novena

Working Hours: 5.5 Days | Mondays to Fridays 9am to 6pm AND Saturdays 9am to 12pm

Salary (commensurate with experience): Up to $5,500 + Performance Bonus + Annual Leave 14 Days + Medical/Dental Benefits $500/year

Duration: Permanent

Industry: Healthcare Industry

Main Responsibilities:
Handle patients’ enquiries and needs
Provide assistance to doctors during consultation session and procedures; including doing venipuncture
Perform counter duties (Registration, Billing and Appointment)
General admin duties
Any other ad hoc duties as assigned

Requirements:
Minimum of ITE & Diploma with minimum of at least 1-2 years of experience
Patient, willing to learn, able to work under minimum supervision
Bilingual in Mandarin and English to communicate with patients who can only speak in Mandarin

Email to: [email protected]

Do visit www.facebook.com/search.personnel for more job listings.

***We do not charge our candidates any referral fee nor bind them with any contract.***

Chloe Ong

Senior Consulting Manager (APAC)

Reg no.: R22105510

EA No: 13C6684

Responsibilities :

• Responsible for the design and development of analog building blocks, including amplifiers, integrators, switched capacitor circuits, regulators, bandgap circuits, Delta-Sigma ADCs, SAR ADCs, filters and control logics etc.
• Responsible for top-level integration of high performance mixed signal chips including analog front end signal acquisition and conditioning chips and analog front end battery monitor chips etc.
• Work with digital team to define register maps, control logics, digital filters for analog front end chips or mixed signal SOCs etc.
• Conduct periodic design reviews.
• Support test development and product development teams in bringing projects to production.

Requirements:

• Degree/Master/PHD in Electrical Engineering or Microelectronics with excellent technical background in analog /Mixed-Signal design.
• With interest in IC design welcomed.
• With experience in analog IC design preferred.
• Salary will be offered base on working experience

Responsibilities :

• Responsible for the design and development of analog building blocks, including amplifiers, integrators, switched capacitor circuits, regulators, bandgap circuits, Delta-Sigma ADCs, SAR ADCs, filters and control logics etc.
• Responsible for top-level integration of high performance mixed signal chips including analog front end signal acquisition and conditioning chips and analog front end battery monitor chips etc.
• Work with digital team to define register maps, control logics, digital filters for analog front end chips or mixed signal SOCs etc.
• Conduct periodic design reviews.
• Support test development and product development teams in bringing projects to production.

Requirements:

• Degree/Master/PHD in Electrical Engineering or Microelectronics with excellent technical background in analog /Mixed-Signal design.
• With interest in IC design welcomed.
• With experience in analog IC design preferred.
• Salary will be offered base on working experience