Total 41 staff nurse job vacancies in Art / Design / Entertainment category in Singapore

Locations: Woodleigh/Paragon

Pay rate for Staff Nurse: $25 / hour (Weekday), $27 / hour (Sat)

Mon to Fri: 9am-5.30pm (with 1 hour break), Sat: 9am-1.30pm

• Assist Doctor in specialist clinic
• Provide primary nursing care and support
• Administer and ensure consistent high quality and personalised service to patients
• Perform any other related nursing duties when required
• Perform front-counter and administrative duties

Requirements:
• Min. Diploma in Nursing or equivalent (recognised by Singapore Nursing Board)
• Registered Nurse with Singapore Nursing Board

Interested and qualified candidates, please send in your application to [email protected]

Ivy Yong Shi Mei

R2198995

Recruit Express Pte Ltd 99C4599

Job Scope:

• Clinic Nursing duties in ENT / Gastro / Healthscreening clinic
• Full jobscope will be shared during interview

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of any nursing experience

Office hours (5.5days)

$3K to $4.2K (depending on exp)

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

Job Scope:

• Clinic Nursing duties in ENT / Gastro / Healthscreening clinic
• Full jobscope will be shared during interview

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of any nursing experience

Office hours (5.5days)

$3K to $4.2K (depending on exp)

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

Job Scope:

• Clinic Nursing duties in ENT / Gastro / Healthscreening clinic
• Full jobscope will be shared during interview

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of any nursing experience

Office hours (5.5days)

$3K to $4.2K (depending on exp)

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

• Run clinic, our clinic use plato system, answering phone calls, making appointments, cheperon, doing simple dressing in clinic, collecting payment.
• Doing some phone calls booking to hospital or radiology department, assist in endoscopy.

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of nursing experience

Jan 2025 to May 2025 (Assingment)

Office hours 5.5days

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

• Run clinic, our clinic use plato system, answering phone calls, making appointments, cheperon, doing simple dressing in clinic, collecting payment.
• Doing some phone calls booking to hospital or radiology department, assist in endoscopy.

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of nursing experience

Jan 2025 to May 2025 (Assingment)

Office hours 5.5days

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.

Staff Engineer, RTL Design

Responsibilities:

We are seeking a talented RTL Engineer to join our team in Singapore. As an RTL Engineer, you'll ensure the highest quality products by developing and implementing robust methodologies. Work alongside a talented team of engineers to deliver innovative solutions that meet the evolving needs of our customers.

Responsibilities

• Own and be responsible for pre-tape out quality for digital SOC modules on the MCU

• Explore architecture and develop micro-architecture.

• RTL development for IPs and SOCs using Verilog

• 3rd party IP identification, selection, and integration

• Collaboration with verification and FPGA teams in test plan development and debug

• Collaborate with the Physical Design team to close the design on timing and power targets

• Assist in silicon bring-up and validation;

• Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues

Requirements

• Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 5-8 years of experience.

• Possess deep and broad knowledge of current and emerging SOC design technologies.

• Have expert knowledge in designing, implementing, and troubleshooting IPs and SOC

• Demonstrate a deep understanding of customer needs and the competitive landscape.

• Ability to estimate the impact of and help plan and lead the implementations and have a positive impact on the entire output

• Can architect and guide programs across the full range of technical areas.

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.

Staff Engineer, Design Verification

Responsibilities:

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.

• Develop test plans at block, sub-system, and chip level.

• Execute SoC-based verification at full-chip.

• Write C-based lib packages and tests.

• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.

• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.

• Automating the test environment for randomized testing and scoreboarding.

• Utilize advanced debugging techniques to identify and resolve design and verification issues.

• Perform root-cause analysis and work with design teams to fix identified issues

• Define and track functional and code coverage metrics to ensure thorough verification.

• Ensure that verification quality meets or exceeds industry standards and project requirements.

• Edge-based AI inference is preferred.

Requirements

• BSEE /MSEE 5-8 years Degree of experience in block, sub-system, and full-chip verification

• Should have delivered multiple chips functioning to Specification.

• Identify and manage verification deliverables, milestones, and schedules.

• Proactively identify potential verification risks and develop mitigation strategies.

• Collaborate with design, architecture, and software teams to understand and verify design intent.

• Communicate verification progress, issues, and results to stakeholders and management.

• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges

• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.

• C-based verification in an SoC environment is required

• Experience with ARM processor-based designs and low-power design techniques is a plus.

• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile

• Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5

• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.

Staff Engineer, Design Verification

Responsibilities:

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.

• Develop test plans at block, sub-system, and chip level.

• Execute SoC-based verification at full-chip.

• Write C-based lib packages and tests.

• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.

• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.

• Automating the test environment for randomized testing and scoreboarding.

• Utilize advanced debugging techniques to identify and resolve design and verification issues.

• Perform root-cause analysis and work with design teams to fix identified issues

• Define and track functional and code coverage metrics to ensure thorough verification.

• Ensure that verification quality meets or exceeds industry standards and project requirements.

• Edge-based AI inference is preferred.

Requirements

• BSEE /MSEE 5-8 years Degree of experience in block, sub-system, and full-chip verification

• Should have delivered multiple chips functioning to Specification.

• Identify and manage verification deliverables, milestones, and schedules.

• Proactively identify potential verification risks and develop mitigation strategies.

• Collaborate with design, architecture, and software teams to understand and verify design intent.

• Communicate verification progress, issues, and results to stakeholders and management.

• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges

• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.

• C-based verification in an SoC environment is required

• Experience with ARM processor-based designs and low-power design techniques is a plus.

• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile

• Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5

• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power

Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and > 5 years of related experience

Skills and responsibilities:

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 5 years or more experience in a relevant field.

Job Scope:

• Clinic Nursing duties in Dermatology / Aesthetic Clinic
• Full jobscope will be shared during interview

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of any nursing experience

Office hours (5.5days)

$3K to $4.3K (depending on exp)

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

Job Scope:

• Clinic Nursing duties in Dermatology / Aesthetic Clinic
• Full jobscope will be shared during interview

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of nursing experience

Office hours (5.5days)

$3K to $4.3K (depending on exp)

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

Job Scope:

• Clinic Nursing duties in Dermatology / Aesthetic Clinic
• Full jobscope will be shared during interview

Requirements:

• Min Diploma in Nursing
• Min 1 to 2 years of nursing experience

Office hours (5.5days)

$3K to $4.3K (depending on exp)

Interested candidates, please send your updated resume to [email protected]

Huang Jingsheng Kevyn
Recruit Express Pte Ltd
Company EA License number: 99C4599
Personnel EA License number: R1333338

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell first revolutionized the digital storage industry by moving information at speeds never thought possible! Today, that same breakthrough innovation remains at the heart of the company's storage, network infrastructure, and wireless connectivity solutions. With leading intellectual property and deep system-level knowledge, Marvell's semiconductor solutions continue to transform the Enterprise, Data Center, SMB, Cloud, Automotive, Industrial, and Consumer markets. You will be solving new technical challenges alongside leading industry professionals in an open, creative environment with plenty of opportunities for personal / professional growth. Join our ambitious team within a multi-nation, multi-cultural company. Marvell develops leading-edge products within a unique high-tech environment that motivates & encourages continued learning and growth!

What You Can Expect

• Designing highly sophisticated CMOS transceiver/SERDES products.
• Implementation and verification of circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets
• Performing design verification using industry standard tools such as Spectre, MATLAB etc.

What We're Looking For

• Master’s degree and/or PhD in Electrical Engineering and 3+ years of experience.
• The ideal candidate should have a deep understanding of analog mixed-signal design with experience in high-speed transceivers.
• Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, Filters
• In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
• Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE
• Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.)
• Familiarity with CDR architectures and implementations
• Design experience in advanced CMOS technologies, design with FinFet technology
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
• Experience in lab testing of high-speed transceivers

Responsibilities:

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.
• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.
• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working.
• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.
• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs.

Requirements:

• Bachelors with min 5 - 8 years relevant industry exp.
• Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products.
• Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/UVM experience.
• Familiar with ASIC verification methodology, tools, and development flow.
• Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO(USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals.

Responsibilities:

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.
• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.
• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working.
• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.
• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs.

Requirements:

• Bachelors with min 5 - 8 years relevant industry exp.
• Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products.
• Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/UVM experience.
• Familiar with ASIC verification methodology, tools, and development flow.
• Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO(USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals.

• We are a chip design service company invested by an international consortium and founded by a senior chip design technical team.
• The company is headquartered in Singapore and will take root in Singapore for long-term development.
• The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.
• We have rich industry experience and deep practical accumulation in ASIC design and business management.

Our office is located in one North and walking distance from MRT.

We Provide competitive salary and compensation package for the right candidate. We are work-life balance and friendly to employees with various benefit.

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered. ( for excellect junior candidates with 3+ years experience will be considerated )

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

Job Description

• Visitor interaction, providing information and assistance
• To assist Navy Museum staff members on the daily Museum operations
• To assist Museum staff members to facilitate school and public programmes
• Will be trained to provide information about the exhibits

Job Requirement

• An interest and passion for Singapore history, museums and the local art scene is an added advantage
• Self-directed learner and problem solver who remains productive under pressure
• Proficient in spoken and written English
• Cultural understanding and empathy for diverse communities
• Service oriented and enjoy interacting with people
• Must be willing to work at Navy Museum Singapore, Address: 112 Tanah Merah Coast Road
• Must be able to work on at least 1 weekend (Saturday or Sunday) every week

Benefits

• Part-Time rate of $12/hour
• Uniform provided.
• Transport provided at EXPO MRT on Sat/Sun and Public Holidays
• Free SDC Adventurer Membership after 1 month deployment

Key Responsibilities:

• Collaborate with the front-end design team to complete chip floorplan, clock architecture, and power plan.
• Take ownership of physical design tasks, including P&R (Place and Route), formal verification, static timing analysis, physical verification, power analysis, and design for reliability.
• Manage the full backend design flow, ensuring that designs meet all specifications and constraints for successful tapeout.
• Research and develop methodologies for advanced process nodes in physical design.
• Build and optimize automated physical design platforms to enhance efficiency.
• Write and maintain scripts (TCL, Perl, or Python) to support design tasks and tool automation.
• Work with EDA tools to perform analysis and optimizations, ensuring the quality of physical design and compliance with industry standards.

Required Qualifications:

• Extensive experience in the digital backend design field, with a focus on physical design, P&R, static timing analysis, and verification.
• Strong expertise in physical design methodologies for advanced process nodes.
• Proficient in scripting languages such as TCL, Perl, or Python to automate tasks and build platforms.
• In-depth knowledge of EDA tools used in physical design, such as Cadence, Synopsys, or Mentor Graphics.
• Experience with design for reliability, power analysis, and physical verification.
• Proven track record of successful tapeouts and deep understanding of the full backend design flow.

Thank you for your application and we regret that only shortlisted applicants will be notified

By submitting any application or resume to us, you will be deemed to have agreed & consented to us collecting, using, retaining & disclosing your personal information to prospective employers with the services provided by us.

EA (18C9514/R23118479)

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Locum to Perm Staff Nurse Positions

Locations:

1. Paragon Positions: 2 Staff Nurses (SN) and 1 Senior Staff Nurse (SSN) for locum to perm (3 months) or purely locum (3 months)
   Requirements: Strong experience in Day Surgery, Operating Theatre (OT), or robust Obstetrics & Gynecology (OG) experience
   
2. Woodleigh Position: 1 Staff Nurse (SN) for locum to perm (3 months)
   Requirements: Experience in Assisted Reproductive Technology (AU)
   

Schedule:

• Weekdays: Monday to Friday, 9:00 AM to 5:30 PM (1-hour break)
• Saturday: 9:00 AM to 1:30 PM

Pay Rates:

• Staff Nurse: $25/hour (Weekdays), $27/hour (Saturday)
• Enrolled Nurse: $21/hour (Weekdays), $23/hour (Saturday)

Conversion to Permanent:

• Salary Range: $3,000 to $5,000+ (based on experience)

How to Apply: Send your resume to Jocelyn Chan at [email protected] or contact via Telegram @jocelynchan.

Jocelyn Chan | Consultant | Recruit Express Pte Ltd (Healthcare & Lifescience) Company EA Licence Number: 99C4599 Personnel EA License: R1331820

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Salary: up to $4200

Working Days & Hours: Mon-Fri office hours, Sat half day

Location: Novena / Orchard / Caldecott

Job Description:

• Provide direct patient care to an assigned group of patients as well as supervise, guide and direct junior nurses assigned to your team.

Job Requirements: Min VALID SNB & BCLS w min 2 yrs of relevant perm inpatient ward experience

Interested candidates, please submit your resume to: [email protected]

Ally Audrey Lok Xin Woon

Recruit Express Pte Ltd (Healthcare & Lifescience)

Company EA Licence number : 99C4599

Personnel EA License: R21102307

[email protected]