Total 14 network engineer job vacancies in Engineering category in Singapore

What you do:

• Generative AI: Language/Multi-modal Model Algorithm Development
  - Transformer-based architecture (LLaMa etc.)
  - RNN and SSM-based architecture (Mamba etc.)
• AI Vison/Voice/NLP/Algorithm Development
• Edge AI (APU) Algorithm Development and Optimization
  - Neural network optimization (Quantization/Pruning/Speculative Decoding)
  - Neural network design automation
• Advanced AI Algorithm: Reinforcement learning (RL), On-device learning

What you bring:

• Familiar with deep learning framework: Tensorflow, Pytorch.
• Familiar with on-device framework for mobile/embedding devices: TFLite, ExecuTorch
• Required programming language: Python, C/C++, Java.
• Knowledge in deep learning and generative AI algorithm/model development/optimization, model training methodology preferred
• It is nice to have experience in developing deep learning and generative AI algorithms for mobile/embedding devices.
• Candidates with more years of experience will be considered for a senior role.

Location: One North, Singapore

Important note: This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.

About the company

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact.

Engineer - Analog / RF Design [Radio System Solutions]

Job Description:

• Design of RF/Analog/Mixed-signal IC circuit blocks / IPs based on specifications (performance, area, power consumption).
• Realize IC layout with floor planning and performance considerations (with layout engineers).
• Testing & Debugging of IC prototypes (with system verification engineers).
• Support of IC to mass production ready.
• Continual support / debug of field related issues or customer IC rejects.
• IC design and performance documentation.

Requirement

• Bachelor's Degree / Master’s Degree in EEE (major in IC Design).
• Knowledge of RF/analog designs through final year project and internship are an added advantage.
• Training will be provided.

Important Note: This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.

About the team

Radio System Solutions Division develops standalone RF-IC or IPs for wireless communication products within MediaTek. This involves designing and verification of building blocks such as low-noise amplifiers, power amplifiers, filters, data-converters, phase-locked loops, low-dropout regulators and digital calibration circuits in advanced semiconductor processes. We are looking for a passionate talent who always up for challenges to join us for this exciting career journey!

In MediaTek, we believe technology changes lives and a changed life can change the world.

Joint us - Tomorrow built by you.

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

What you will do

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek:

• Scan chain insertion & ATPG pattern generation
• Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
• Diagnosis to help manufacture process improvement

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:

• PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
• Develop & integrate DFT-related RTL design modules to test chip

What you will bring

1. Master's Degree in EEE/ EE/ CE
2. Expertise in Synopsys and/or Mentor DFT tools, and HDL simulators like Synopsys VCS
3. Fluency in script language including but not limited to TCL/Perl/Python
4. Experience about MBIST with state-of-the-art SRAM structure & EDA tools is big plus
5. Skill for RTL design & integration, and physical failure analysis(PFA) will also be plus
6. Ability to think and work independently with different teams
7. Interest in understanding more details in entire design flow
8. Ability to use English for discussing technical details
9. More than 4-year industrial work experience is preferred

What you do

Be part of the team that validates the physical sign-off of our chips, powering the brands we love every year with 2 billion consumer electronic products such as digital TVs, home audio devices, DVD/Blue-ray players, smartphones, tablets, networking and connectivity products, and many more. As a member of the MediaTek Physical Verification Sign-off team, you will be responsible for ensuring the manufacturability and reliability of IC designs through rigorous physical verification processes to enable the success of our chips tape-out. Join us in shaping the future of technology and making a real impact on the world!

• Responsible for assembling of various design system into a full chip.
• Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.
• Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and schematic of the IC design.
• Execute electrical rule check (ERC) to identify potential electrical issues and ensure the integrity of the design.
• Perform antenna and electrostatic discharge (ESD) checks to prevent potential reliability, latch-up, leakage issues.
• Collaborate with design and layout teams to address and resolve physical design issues and optimize the layout for manufacturability and reliability.
• Contribute to the development and improvement of physical verification methodologies and flows.
• Work closely with process technology teams to understand and address process-related challenges and constraints.
• Participate in tape-out activities and ensure that the physical design meets the required quality and reliability standards for fabrication.

What you bring

• With minimum 8 years of relevant experience.tronic Engineering / Computer Science or equivalent..
• With minimum 8 years of relevant experience
• Solid understanding of physical design concepts, IC manufacturing processes, and semiconductor device physics.
• Proficiency in using physical verification tools such as Calibre, IC Validator, or other industry-standard DRC/LVS tools.
• Experience with scripting languages such as TCL, Perl, or Python for automation and tool customization.
• Strong problem-solving skills and the ability to analyze and debug complex physical design issues.
• Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
• Familiarity with EDA (Electronic Design Automation) tools and design methodologies is a plus.
• Proficient in UNIX (Linux) platforms.
• Strong communication skills, problem solving and analytical skills.

Location: One North, Singapore

Who We Are

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.
  

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. 2 years of relevant experience in similar field.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. of 8 years of relevant verification experiences.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

Overview

We are looking for result-driven candidates who would thrive under a fast-pace working environment and having a strong desire to make an impact in their organization.

What you will do

• Own the entire layout implementation process: schedule estimation, floorplanning, layout construction, physical verification and memory compiler leaf-cell creation
• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely with multi-functional members to optimize layout realization according to the desired power, performance and area optimization requirement
• Candidates with strong soft skills could be tasked to undertake project management, coaching of new hires/interns or workflow improvement initiative

What you bring

• Bachelor’s degree in Electrical/Electronic/Computer Engineering or equivalent
• At least 8~10 years of direct experience in custom Memory layout implementation (SRAM/ROM/TCAM/CIM) in advanced finFET/GAA process nodes
• Proficient in understanding DRM of advanced CMOS technologies and have a good understanding of deep sub-micron and DFM issues (eg. WPE, LOD effects, etc.)
• Strong knowledge in floor-planningtechniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integrationflow
• Strong knowledge in executing and debugging various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc
• Proficient in Synopsys/Cadence layout editors
• Ability in script programming (eg. Python, Tcl, Perl or C-shell) is a plus
• Team player and effective in cross-team communication and time management

Location: One North, Singapore

Why MediaTek

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

The Job

• Develop timing/power/noise characterization flow for advanced node memory compiler.
• Strong focus on design automation for SRAM compiler, big data analysis and design verification.
• Develop memory analysis flow for PPA check.

The Talent

• Bachelor's Degree (with min. 6 years of relevant industry experience) /Masters Degree (with min. 4 years of relevant industry experience)/ PhD in Electrical and Electronic Engineering/Computer Engineering/Computer Science.
• Knowledge of SRAM/ROM memory functionality and high speed, low power memory design architecture.
• Experience in spice simulation and understand CMOS layout view, Verilog coding is preferable.
• Proficient in script programming with Perl or Python3.

What you will do

• Responsible for Standard Cell Library Characterization for leading edge process node (7nm/5nm/4nm/3nm), as the pioneer to setup design platform for Mediatek projects.
• Perform timing/power/constraint/noise/variation modeling, analysis and flow development for >15K logic circuit for one process node.
• Testchip design and Si data analysis flow development for advanced technology node (<7nm), including big data processing and visualization.

What you bring

• BS/MS in Engineering/Computer Engineering/Computer Science.
• Basic knowledge of IC design and circuit design.
• Basic knowledge of UNIX/LINUX environment and any programming language, e.g. Python, Perl, Tcl, C/C++.
• Familiar with foundation IP (Std-cell, Memory, I/O) design and/or CAD is a plus.
• Knowledge of spice simulation, data analysis, machine learning is a plus.

Location: One North, Singapore

What you do:

• Generative AI: Language/Multi-modal Model Algorithm Development
  - Transformer-based architecture (LLaMa etc.)
  - RNN and SSM-based architecture (Mamba etc.)
• AI Vison/Voice/NLP/Algorithm Development
• Edge AI (APU) Algorithm Development and Optimization
  - Neural network optimization (Quantization/Pruning/Speculative Decoding)
  - Neural network design automation
• Advanced AI Algorithm: Reinforcement learning (RL), On-device learning

What you bring:

• Familiar with deep learning framework: Tensorflow, Pytorch.
• Familiar with on-device framework for mobile/embedding devices: TFLite, ExecuTorch
• Required programming language: Python, C/C++, Java.
• 2+ years experience in deep learning and generative AI algorithm/model development/optimization, model training methodology.
• It is nice to have experience in developing deep learning and generative AI algorithms for mobile/embedding devices.
• Candidates with more years of experience will be considered for a senior role.

Overview

We are looking for result-driven candidates who would thrive under a fast-pace working environment and having a strong desire to make an impact in their organization.

What you will do

• Own the entire layout implementation process: schedule estimation, floorplanning, layout construction, physical verification and memory compiler leaf-cell creation
• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely with multi-functional members to optimize layout realization according to the desired power, performance and area optimization requirement
• Candidates with strong soft skills could be tasked to undertake project management, coaching of new hires/interns or workflow improvement initiative

What you will bring

• Bachelor’s degree in Electrical/Electronic/Computer Engineering or equivalent
• At least 8~10 years of direct experience in custom Memory layout implementation (SRAM/ROM/TCAM/CIM) in advanced finFET/GAA process nodes
• Proficient in understanding DRM of advanced CMOS technologies and have a good understanding of deep sub-micron and DFM issues (eg. WPE, LOD effects, etc.)
• Strong knowledge in floor-planningtechniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integrationflow
• Strong knowledge in executing and debugging various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.
• Proficient in Synopsys/Cadence layout editors
• Ability in script programming (eg. Python, Tcl, Perl or C-shell) is a plus
• Team player and effective in cross-team communication and time management

Location: One North, Singapore

Why MediaTek

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Job Description:

• Perform CPU design integration and IP development for ARM based CPU subsystem.
• Derive and develop Application or Subsystem PPA (Performance, Power, Area) optimization initiatives.
• Support SoC in MCUSYS Subsystem from Technical Feasibility Evaluation phase to Post-Silicon debug phase.

Job Requirement:

• Bachelor's Degree/Master's Degree in Electrical/Computer Engineering.
• Min 10 years of CPU related Architect/ RTL/ Verification/ Implementation design experience.
• Familiarity with ARM/MIPS/SNPS ARC CPUs.
• Cross-site working experience is a MUST.
• Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.
• Smart-Phone Adv. ASIC consumer product HW design experience is a PLUS.

Responsibilities:

• Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS.
• Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP.
• Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

Requirement:

At least 4 years of experience in Physical Design and Signoff

[Skills]

>> Synthesis::

PPA improvement through synthesis recipe exploration for better perf, power, and area.

>> Physical design ::

Floor Planning, Place & Route followed by Timing and Physical Closure

>> Signoff ::

PI : PG mesh spec selection, Bump/RDL planning, IR closure

PV : DRC, LVS, ANT, ERC closure

STA : Block level timing closure