Total 100 quality control engineer job vacancies in Engineering category in Singapore

You are responsible for, but are not limited to, the following:

• Develop and optimize unit processes to meet the yield and quality requirements of advanced Replacement Gate 3D NAND parts
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement
• Prioritize within Singapore based manufacturing Dry Etch team on the key technology issues that need R&D breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement
• Participate with Boise R&D peers on technology choices for the upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Identify process simplification opportunities and drive multi-functional teams in implementation
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Provide advice and counsel to management on significant technical issues. Lead and initiate ground breaking projects through patents/technical papers.
• Communicate and collaborate with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a requirement.
• Be part of the continuous worldwide R&D engagement with suppliers pushing for breakthrough solutions.

You should possess

• Masters/PhD in Electrical & Electronics, Chemical, Mechanical, Materials Engineering.
• Strong aptitude for research and development and ability to create production-worthy technologies.
• Ability to develop and maintain relations with multi-functional teams and vendors.
• Strong communication skills (written, verbal and presentation).
• Highly motivated and adaptable to our demanding, dynamic and rapidly changing work environment; flexibility to work for extended hours, as required.
• Ability to travel to US R&D site for few months to engage in collaborative R&D work.

As an EUV Photo Project Engineer in Operation Central Team (OCT) Central Process and Equipment Engineering (CPEE) Photo Scanner at Micron Technology, Inc., you will lead project activities to achieve and maintain outstanding EUV Ecosystem in high volume manufacturing.

You will be responsible for providing leadership to the global Micron network to drive Photo EUV Productivity, Hardware, Application, Value Engineering, Continuous Improvement Program, Cost reduction, TOR and BKM governance through technical expertise, business process management and project execution.
You'll be working closely with various teams like Process Equipment Engineering Groups, Technology Development, Procurement, and the Central Team, as well as interacting with equipment suppliers to address manufacturing issues. Effective collaboration with manufacturing sites, Quality Engineering, and other functional departments is key, with an exciting element of international travel to achieve your goals.
It’s a great opportunity for someone who enjoys challenges in State of Art Technology in EUV, teamwork and global experiences!

Responsibilities:

• Ensure a safety-first culture for all program and project solutions.
• Oversee the EUV Litho Cluster, including Scanner and Track installation, to meet TIQ (Tool Installation Qualification) goals.
• Close collaboration with EUV ecosystem suppliers (ASML, TEL, Edward Zenith, Zinter, etc) and internal partners (HVM fabs, Central Teams, Technology Development teams).
• Manage EUV Reticle support tools (e.g., Reticle inspection tools, Reticle Clean tools, EUV Reticle pod storage, Pod Clean tools etc) through closed collaboration with Fab and Central Reticle Teams.
• Drive EUV Industrialization goals by leading Supplier Workstream Programs (Eg: Scanner, Source, Drive Laser, TEL Track etc) to achieve industry outstanding performance in Imaging, Overlay, Rework, Defectivity, and Efficiency (Wafers Per Day).
• Drive and facilitate Governance meetings and cross-collaboration projects with internal and external partners to achieve Micron Strategic Initiatives (Eg: cost, yield, quality, Maxout, environmental sustainability).
• Demonstrate strong communication and reporting skills to provide regular Executive updates on project progress, challenges, and escalation for resource support.
• Oversee processes, guide initiatives, and lead project team members toward goal achievement using analytical skills and problem-solving techniques.
• Proactively identify bottlenecks, drive improvements, and share standard methodologies across HVM fabs.
• Demonstrate ownership and accountability in delivering results.

Requirements:

• Global Factory Network Expertise: Demonstrated understanding of worldwide high-volume manufacturing network operations across different geographical region.
• Leadership and Strategic Initiatives: Proven ability in team development and leading transformative initiatives.
• Manufacturing Knowledge: Familiarity with Front End (FE) manufacturing, reticle manufacturing, and fab processes.
• Project/Resource Management: Ability to manage Global Project and Resource.
• Effective Communication: Skilled at communicating effectively across various organizational levels.
• Customer-Focused Project Management: Proficient in project management with a strong customer focus.
• Continuous Learning Advocate: Continuous learning on the job and provide technical mentoring for peers.
• Minimum 4 years’ experience working as Photolithography Equipment/ Process Engineer or Photo Scanner Engineer in Wafer Fab. ASML EUV Scanner experience will be an advantage
• Bachelors/master’s degree in Electrical, Electronics, Mechanical Engineering

You will be responsible for providing leadership to the global Micron network to drive Photo EUV Productivity, Hardware, Application, Value Engineering, Continuous Improvement Program, Cost reduction, TOR and BKM governance through technical expertise, business process management and project execution.
You'll be working closely with various teams like Process Equipment Engineering Groups, Technology Development, Procurement, and the Central Team, as well as interacting with equipment suppliers to address manufacturing issues. Effective collaboration with manufacturing sites, Quality Engineering, and other functional departments is key, with an exciting element of international travel to achieve your goals.
It’s a great opportunity for someone who enjoys challenges in State of Art Technology in EUV, teamwork and global experiences!

Responsibilities

• Develop and optimize unit processes to meet the yield and quality requirements of advanced NAND part type
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement Prioritize within Singapore based manufacturing Wet Etch team on the key technology issues that need TD breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement Participate with Boise TD peers on technology choices for the upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work with manufacturing and Boise TD to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Initiate and manage experiments to widen process margins as well as to test out manufacturability of next node solutions
• Identify process simplification opportunities and drive cross functional teams in implementation Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Serve as a technical expert within Micron contributing to technical projects for improvements to processes, procedures and equipment.
• Lead team or sites or suppliers on complex, multi-disciplinary projects in quality focused meetings, process and yield improvement meetings, cost and productivity improvement meetings
• Provide advice and counsel to management on significant technical issues. Leads and initiate innovation projects through patents/technical papers.
• This position requires communications and collaboration with partners both locally and globally.
• Strict adherence to Micron Intellectual Property protection policy is a must.

Be part of the continuous worldwide TD engagement with suppliers pushing for breakthrough solutions.

Requirements

• Masters/PhD graduates in Materials Science, Chemical/Microelectronic Engineering or Chemistry are welcomed to apply.
• A deep understanding of chemistry, chemical kinetics, thermodynamics and mass transport
• 2-3 years of experience in Semiconductor Equipment/Process development is preferable
• An understanding of the general process steps and process flow for memory processing, planar and vertical NAND memory in particular.
• Working knowledge of data analysis systems e.g.: Y3 to facilitate analysis of experimental data
• Working knowledge of Design of Experiments (DoE) Proven ability to collaborate with local and overseas teams on projects
• Excellent oral and written communication skills with ability to convey the message in concise and effective manner both in local as well as remote communications.
• Ability to be a self-motivated individual and be adaptable to Micron’s changing needs in terms of working extended hours, if required Proven ability to work in a demanding & dynamic environment and able to prioritize and manage multiple projects simultaneously
• Ability to travel for extended periods of time and stay at Boise TD for 2-4 months at a stretch to work on technology development.

When you join MSB Industrial Engineer (IE) team, you will be learning the skills for capacity modeling, capital planning & execution and factory commit. In the course of work, you'll be exposed to counterparts from a diverse range of backgrounds and teams and will have opportunity for contributing to the organization while learning from each other. You're also part of the team that produce data and analyses supporting factory critical metrics decision making that include (but not exhaustively) capital expenditure, loading (revenue) commit and equipment performance improvement activity, Some aspects of the work are below

Modeling

• Perform line study for setting up capacity model
• Apply statistical analysis to acquire model parameters and Factory Operation related buffer strategy
• Work with relevant teams for auditing and updating model parameters (utilization, UPH, overhead, etc)
• Maintain Factory Planning Master Data in a manner that supports capacity analysis, factory scheduling, supply planning and multi-functional reporting needs
• Use Microsoft Excel and other applications to supplement standard model for quick turn-around analysis

Strategic Planning

• Maintain robust database of key improvement activities and equipment delivery
• Perform capacity analysis loading plan for setting boundary condition, submitting capital requirement and requesting key activities for throughput improvement
• Perform bottoms-up analyses of approved loading and modeling changes
• Coordinate space planning for incoming tool with facility, relevant equipment and manufacturing team members
• Engage in factory space optimization and network capital optimization by identifying under-utilized/obsolete capacity for transfer, re-sale and/or scrap

Factory Commit

• Engage in weekly factory commit activity in collaboration with Factory Planning and Operation teams (current quarter / rolling 13 weeks), and Central Planning teams (up to 9 months)
• Submit equipment and tooling purchase request and coordinate downstream activities: PO release, space enablement, delivery and production release
• Comprehend Tactical Operation constraint in identifying dynamic constraint workstation for robust factory loading commit
• Collaborate with Strategic Scenario and Capital Planning team on investigation of tactical boundary condition comparison with strategic boundary condition

Capital Planning

• Take charge of capacity related capital and Off-Capital items through capital lifecycle: proposal à disposal through appropriate business process and in timely manner
• Strive for capital optimization through network balancing
• Maintain capital related information in system and offline database for own area (capacity and non-capacity related) in robust manner

Space Planning

• Collaborate with Facility IE team on detailed space enablement plan for incoming tools
• Maintain database of incoming and excess tool list for communication with Facility IE

Reporting

• Understand assumptions in reports and use them effectively
• Develop and maintain reports that effectively communicate capacity information

Project Management

• Run regular meeting, take meeting minutes, record action items and ensure closed-loop and accurate completion of action items
• Use established project management approach and methodology when serving as project manager

Continuous Improvement

• Possess a continuous improvement process (CIP) approach where you are always looking for ways to improve current way of doing things
• Apply new (e.g. RPA, Tableau, Power BI) and traditional (Excel, VBA) methods to improve and automate tasks & visualization in the planning system/models

Compliance

• Finishes the required training timely
• Conducts all work in accordance with Micron EHS (Environment, Health, Safety) and ethics policies
• Provide timely feedback when quality, safety, or ethical issues arise

Requirements:

• Degree in Industrial/Mechanical/Computer Engineering and Computer Science preferable
• With at least 2 years of CCA in university, preferably in leadership positions.
• Good in written communication and presentation skills.
• Highly motivated to work in a dynamic environment, with good integrity and character.
• Programming skill will be an added advantage.
• Ability to quickly analyze situations, identify issues, and develop effective solutions under tight deadlines.
• Demonstrated capacity to maintain composure and productivity in high-pressure environments, adapting to changing priorities and challenges.
• Proven ability to prioritize tasks, manage numerous projects simultaneously, and meet deadlines without compromising quality.
• Previous internship experience in a related field, demonstrating practical application of skills and knowledge in a professional setting will be an added advantage.
• Keen in semiconductor industry
• Possess advanced Literacy and Numeracy skills

As NAND Sg Process Development (PD) Program Management Engineer, you will support the Program Manager, in his collaboration work with Technology Development (TD) peers, High Volume Manufacturing (HVM) Fabs, Operations Central Teams (OCT) and other stakeholders to drive best in class performances and all critical initiatives for NAND nodes to meet program milestones.

You will play a key role in establishing and managing cost programs to meet allocated capital expenditure budget, operational expenditure cost management; and deliver node-over-node cost per gigabit (CPGB) reduction targets meeting business requirements.

You will work in a fast-paced environment with the world’s Best NAND TD team in a role that is highly Collaborative and requires a great deal of Customer Focus; continuous improvement and an Innovative growth mindset are required to achieve desired results. You will work within a Process Development organization alongside leaders and engineers from Fab functional Process Areas.

Responsibilities:

• Regular interaction with PD/PI team for MOR Updates/Tracking in close collaboration with Industrial Engineering (IE) Modeling Team.
• Drive alignment and timely delivery of results on critical projects, manage execution of TD roadmaps/strategies to meet milestones.
• Drive continuous improvement of PMI/SPC from process areas, publish roadmaps, highlight risks and mitigate.
• Prequal Expense: Work with stakeholders to drive prequal expense reduction (materials, spares etc).
• TD-University Engagements: Engage with Talent Acquisition teams to initiate/support initiatives to build strong TD talent pipelines.
• EBD Grants: Collaborate with Finance Team to comply with regular submissions and meet yearly audits.
• Additional portfolio includes Micron Voice Engagements, managing Dept budget, compliance with NMI processes, related TD audits and new scopes along the way that contribute to NAND program successes.

Successful candidates for this position will have:

• Bachelor/Masters in related Engineering fields.
• Familiar with both TD and manufacturing environment and business processes
• Extremely strong organizational and communication skills.
• Strong interpersonal skills for smooth collaboration with cross-functional teams.
• Solid communication skills for cross department alignment and providing clarity to leadership and executive teams.
• Highly motivated and adaptable to our demanding, dynamic and rapidly changing work environment.

We are looking for a highly motivated, ambitious, result driven individual with strong work ethic and integrity to join us as a Photolithography Process Development Engineer/Senior Engineer in NAND Technology Integration (NTI) R&D group. You will be using state of the art equipment to support activities associated with rapid deployment of technology nodes, process margin improvement activities and ensure extended engagement with manufacturing on the upcoming technology nodes.

You are responsible for, but are not limited to, the following:

• Develop and optimize lithography processes to meet yield and quality requirements of advanced Replacement Gate 3D NAND parts
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement
• Prioritize within Singapore based manufacturing photolithography team on the key technology issues that need R&D breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement
• Collaborate with Boise R&D peers on technology adaptation and cost optimization towards upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Identify process simplification opportunities and drive multi-functional teams in implementation
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Provide advice and counsel to management on significant technical issues. Lead and initiate ground breaking projects through patents/technical papers.
• Communicate and collaborate with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a requirement.
• Be part of the continuous worldwide R&D engagement with suppliers pushing for breakthrough.

You should possess

• Masters/PhD in Electrical & Electronics, Chemical, Mechanical, Materials Engineering.
• Strong aptitude for research and development and ability to create production-worthy technologies.
• Ability to develop and maintain relations with multi-functional teams and vendors.
• Strong communication skills (written, verbal and presentation).
• Highly motivated and adaptable to demanding, dynamic and rapidly changing work environment; flexibility to work for extended hours, as required.
• Ability to travel to US R&D site for few months to engage in collaborative R&D work.

Possess the above qualities ? Join Us !

Your primary responsibilities will be:

• Risk assessment of NAND cell reliability, identification of the process/trim/test strategy to bridge the gaps for JEDEC and internal product qualification.
• Design experiments to identify and segment the limiting reliability mechanisms impacting NAND quality.
• Design high volume electrical experiments (both wafer level and component level) and perform statistical data analysis to validate process/trims solutions required to close reliability gaps.
• Update management and provide continuous feedback to process development and product engineers on the NAND reliability status and roadmap to bridge gaps.
• Contribute to develop forward looking technology path finding for next NAND generation, including reliability risk assessment and product capability projections, identify innovative design and product features required to meet quality specification.

Required skills:

• Proven experience with NAND device structures, operations and algorithms
• Knowledge and understanding of electrical properties of semiconductor and insulator materials, semiconductor device physics and solid-state physics
• In-depth understanding of physics-based modeling of non-volatile memory and semiconductor devices failure mechanisms, reliability analysis
• Knowledge and understanding of statistical analysis and numerical computing software (Matlab, Octave, JMP)
• Knowledge and ability of scripting languages (C, C++, Matlab, Perl)
• Familiar with Big Data and database queries
• Knowledge of JEDEC standards

Working location:

• 1, North Coast Drive, Singapore 757432

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

FE Central Product Integration Engineering (CPIE) HPM PI Engineer

As FE CPIE HPM (High Performance Memory) PI Engineer at Micron Technology, Inc., you will be responsible for working with global Micron network to drive HPM Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution.

Responsibilities and Tasks

• Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering.
• Active engagement with PI Loop taskforce and/or team in network to address yield and quality challenges, optimize process flow in a timely manner to achieve BIC yield performance.
• Maintain and enhance domain knowledge and technical expertise, explore innovation opportunities with strategic thinking and systematic approach.
• Maintain a strong and open relationship with peer group and managers in other functional areas within central team and outside in areas such as Fab, TD, Product Engineering, GQ. Communicate and respond to issues in a timely manner. Help drive to fix the issue where necessary.
• Demonstrate ability to give effective presentations to both small and large groups on project updates and new initiative proposals.
• Periodically follow up with manager to ensure all type of goals are met and get assistance to remove obstacles.
• Travel to Micron Fab locations as necessary for face-to-face collaboration for program requirements.

Requirements

• Background in electrical engineering, materials science, transistor physics and semiconductor process knowledge.
• Experience with Semiconductor Device Physics, DRAM operations, wafer fabrication process flows, parametric/electrical test, and probe yield will be an added benefit to this position.
• Good data analysis, troubleshoot, problem solving, reporting and presentation skills.
• Good multi-tasking, verbal, and written communication skills.
• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.
• Good organizational capabilities and ability to work effectively with minimal supervision.
• Intermediate to advanced PC skills including Microsoft Office.
• Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities.
• Travel Required: Yes. Willing to travel as needed to support department goals
• Travel Frequency: 20-50%.

Education

• Bachelor’s degree and above in Electrical Engineering, Microelectronics, Physics, Chemistry, Materials Science or related field of study

As a Senior- level Device Engineer in Micron's Front End Central Process Integration Engineering (cPIE) team, you will co-work with the global Micron network on improving Device performance to meet product yield and quality requirements, through optimizing process steps, reducing device variability, optimizing design layout or test specs, and standardizing device engineering business process and working methodology. The primary focus could be either DRAM or NAND flash memory when needed.

Requirements:

• Bachelor's degree with a minimum 5 years of relevant working experience is required. Master's or Ph.D. degree in Physics or Engineering areas is preferred.
• Working experience in fab process or process integration or test engineering. Direct experience in CMOS or NAND/DRAM memory device engineering is preferable.
• Require proven knowledge in semiconductor physics and understanding of transistor operations, scaling limitations and reliability, basic knowledge of CMOS circuits and characterization methods. Experience in advance transistor architectures such as High-K metal gate or FinFET or GAA is preferred.
• Deep understanding of at least one semiconductor fabrication process area, including tool sets, process mechanism, tuning knobs, etc.
• Excellent data analysis skills using at least one software (JMP, SPOTFIRE, etc).
• Strong task ownership, self-motivated to work with other team members to make progress collaboratively.
• Open-minded attitude to learn new skills and could adapt to new working environment swiftly.
• Good communication skills. Proficient in English (speaking and written). Working-level communication capability in Mandarin Chinese OR Japanese is preferred.
• Good digital literacy with MS office. Programming capability such as Python is a plus.
• Occasional domestic and international business travel is required.

Job responsibility:

cPIE Device Engineer, responsible for product yield and quality improvement, by working collaboratively with Micron global network, to improve device performance, standardize business procedure and working methodology.

Your primary responsibilities will be:

• Risk assessment of NAND cell reliability, identification of the process/trim/test strategy to bridge the gaps for JEDEC and internal product qualification.
• Design experiments to identify and segment the limiting reliability mechanisms impacting NAND quality.
• Design high volume electrical experiments (both wafer level and component level) and perform statistical data analysis to validate process/trims solutions required to close reliability gaps.
• Update management and provide continuous feedback to process development and product engineers on the NAND reliability status and roadmap to bridge gaps.
• Contribute to develop forward looking technology path finding for next NAND generation, including reliability risk assessment and product capability projections, identify innovative design and product features required to meet quality specification.

Required skills:

• Proven experience with NAND device structures, operations and algorithms
• Knowledge and understanding of electrical properties of semiconductor and insulator materials, semiconductor device physics and solid-state physics
• In-depth understanding of physics-based modeling of non-volatile memory and semiconductor devices failure mechanisms, reliability analysis
• Knowledge and understanding of statistical analysis and numerical computing software (Matlab, Octave, JMP)
• Knowledge and ability of scripting languages (C, C++, Matlab, Perl)
• Familiar with Big Data and database queries
• Knowledge of JEDEC standards

Excellent execution on assembly process for 1st NPI success and smooth transfer process from NPI to HVM

• Excellent execution of the qualification of NPI products / packages build that proliferate from the pilot products and packages according to planned timeline
• Full responsible on support NPI business process with process TRA, POS, PFMEA/QCP, risk mitigation and documentations.
• Deliver BIC yield and cost on product NPI with integration of DFx BIC package solution, process guideline and design rules.
• Collaboration with multi-functional team from NPI to LVM/HVM process transfer.
• On-time execution of NPI Customer samples and Engineering Samples build for new products and package

SME Process Owner Responsible for Continuous Improvement on Process Yield, Defect Elimination and Process Characterization

• Process owner to perform on-time detection with data analysis for process yield improvement. Lead the defect elimination and continue improvement action, with problem solving methodology, statistical analysis and integration solution decision.
• Process owner to develop process recipe for BIC UPH, conducting process characterization to define process parameters and boundary.
• Continuous develop in depth assembly process technical knowledge, well understand process capability/tolerance//spec limit/CpK, and apply key tools PFMEA/QCP/APC/FDC/Alarm on assembly processes Cz/Development/NPI.
• Global leader for cross team collaboration on network BKM, process recipe spec and recipe standardization/conversion.

Technology enablement and development – Process, Material, Equipment

• Participate and support Product Roadmap, to enable key process capability and technology development to ensure packaging solution is ready prior 1st Qual Silicon deliver.
• Frequent engagement with equipment and material supplier (at least interval of monthly or daily/weekly for process issues)
• Collaboration with Supplier and involvement Supplier Roadmap (Material/Equipment/OSAT), to understand market trends and competitor’s direction, ensure key process technology and capability enablement is in-line.
• Frequent review and participant Competitor Analysis, to understand market trends and competitor’s technology/capability boundary
• Engage and follow PDE business process (TGR, TORB, KEG interlock) for new technology qualification, alignment and safe launch

Teamwork and General expectation

• Trainer/Buddy/Mentor for new team members, build effective relationships within team and cross team (peers, counterpart)
• Regularly review data and direction with supervisor. Demonstrate sound data analysis and judgment. Present reports and findings with appropriate conclusions, recommendations and decision making.
• Develop, or coordinate development of, training materials for existing/new process
• Safety Identify and promptly report hazards, follow safety procedures and area work rules including proper PPE, lockout and chemical safety.

Requirements:

• Bachelors/ Masters in Engineering
  
• Showcase leadership experience/potential
  
• Have engaged in projects during internships
• Great teammate
  
• Showcase critical thinking
• Keen interest in Semiconductor industry
  

Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

Responsibilities :

Equipment Performance

• Come up with methodologies to improve %UD/SD performance globally.
• Design Tier 2/3 matrices to improve %UD/SD.
• Develop suitable global reports for sites to benchmark against each other on %UD/SD
• Design and implement a process to improve workstations MOR %UTIL through %MA & Lost time improvement.
• Study the wafer path taken in critical workstations.
• Identify key data that needs to be extracted from the tool EDA system to map the time taken to complete wafer processing.
• Collaborate with SMAI to build a system to compare the wafer processing time between tools within a workstation.
• Quantify capex avoidance/savings that arise from improving Equipment Performance.

Address Tool to Tool mismatches in Process Areas

• Build a database of inputs for all process areas to address tool to tool mismatch proactively.
• Database of inputs should cover the cross matching of software, hardware & process related inputs.
• Collaborate with SMAI to build a system using these inputs to identify & fix tool to tool mismatches in a workstation.
• Appropriate measures, processes, and metrics should be devised to handle and maintain tool to tool mismatches effectively.

Standardization of practices & BKMs in Process Areas

• Setup global area alignment teams to address chronic issues, drive improvements & eliminate wastes.
• Channel improvements and lessons learnt established from various forums, eg. TPM Forum, Excursion Review, etc.  into global area forums to decide on the standards for deployment, implementation and audit.
• Design suitable matrices for each process area so that improvements impact the 4 pillars.
• Create a library of area level BKMs for Equipment & Process Engineers to search for standards involving the setup of Equipment & associated processes.
• This library must also serve the purpose to feed-forward area level BKMs to TD for process development & HVM for improvement work that will impact the 4 pillars.
• Sit in transfer reviews to ensure N-1 standards are fed-forward to N technode for sustenance

Demonstrate Leadership

• Adopt benchmarking and deliver strategies to close the gaps.
• Challenge complacency and do not let strong market conditions give a false sense of reality.
• Gain insights into the competitor's culture, approach, and capabilities.
• Understand that the only way to guarantee our future is to be the best.
• Understand the challenges your team faces.
• Don’t underestimate the effort it takes to be number one.
• Ignite the passion in people to achieve the impossible.
• Dare to set high targets, expect innovation and breakthroughs.
• Give honest, tough, but productive feedback to the team, and be willing to receive it yourself.
• Challenge others and be willing to stand for something.
• Have the courage to turn a crisis into an opportunity.
• Lead from the front and lead by example.
• Become the team that will out-innovate and out-execute the competition. Don’t accept anything less.
• Be unrelenting and “unreasonable”.
• Cultivate a habit of winning. Winning breed’s confidence.
• Find top talent willing to take risk and support them in doing the exceptional.
• Face unsolvable problems head-on and turn them into opportunities.
• Develop teams and team members to enable them to reach their full potential and reward them accordingly.
• Support team members with coaches and mentors who push TM outside their comfort zone.
• Lead the team to success.
• Leave a legacy behind that we are proud of.
• Believe in your team.

Requirements :

• Bachelors Degree in Electrical / Electronics / Semiconductor Engineering
• 10 years of experience and/or demonstrated ability in any of the following Field (Equipment or/& Process)
• Preferably experienced in Photo & PCVD area.
• Applicants must have a consistent record to collaborate globally and influence by indirect leadership in order to drive resourcing to critical projects across Micron.
• Applicants must have a shown capability in dealing with complexity and an ability to apply resources effectively to bring clarity to required actions.
• Applicants must hold a record of performance excellence for current area of responsibility; and are recognized as having demonstrated successful leadership characteristics both in present and past jobs.
• Applicants are viewed by current reports as an excellent mentor, team builder and motivator.
• Applicants must have demonstrated the ability to solve problems across multi-functional groups, both within and outside their department/Site.
• Applicants must have experience handling large, multi-layer groups that encompass a variety of fields.
• Applicants must have proficiency in handling through systems, informing, organizational agility, dealing with ambiguity, and listening. They must demonstrate a strong alignment with Micron Behaviors and the skills they'll use every day.

As a Senior NAND Cell Device Engineer, in the Singapore Device Technology Development group of Micron Technology Inc., you will be responsible for electrical characterization of the NAND memory cell and develop novel device solutions for cutting-edge 3D-NAND flash technologies. You will have an exciting opportunity to develop best-in class non-volatile memories and products in the world!

Job responsibilities:

• Develop an understanding of performance & reliability requirements for new NAND cells and help refine requirements, as necessary.
• Characterize NAND Memory cell and array properties to identify device improvement directions.
• Analyse automated tester data to establish product qualification gaps, identify new device corners and improve detection capabilities.
• Contribute to the architecture and process definition for state-of-the-art NAND cell, by providing expertise in NAND device physics and array operation.
• Collaborate effectively with process, integration, product, and design engineers, to address NAND memory cell deficits and deliver improvement roadmaps.

Requirements:

• M.S or Ph.D. in Electrical or Electronics Engineering, Physics or Materials Science Engineering or similar.
• 3+ years of work experience in CMOS or non-volatile memory is preferred.
• Deep understanding of semiconductor device physics and processes.
• Knowledge of statistical methods for experiment design and data analysis.
• Solid communication and reporting abilities.
• The ability to be highly skilled at driving for results.

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities

• Leading the design, development and characterization of new tools and identifying and closing any hardware and procedural gaps.
• Innovate solutions that enable best in class performance
• Oversee installation and upgrades of tools ensuring quality of work, cost control and alignment to project schedule.
• Engage equipment vendors to improve current products and implement roadmap needs.
• Work with Process Engineers, Manufacturing, Procurement, and Vendor partners to develop a comprehensive package capable for our volume manufacturing sites.
• Generating and maintaining documents that outline equipment performance, operating procedures, maintenance specifications, and cost metrics.
• Support Internal And External Audits

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above

Location: Fab10N

Closing Date: Until filled

Description

As a NAND CMOS Process Integration Engineer in the Singapore Technology Development department at Micron Technology Inc., you will be responsible for developing 3D NAND CMOS devices scaling and enhancing their performance, reliability and manufacturability.

Responsibilities:

• Develop and innovate critical CMOS modules. Drive multi-functional teams to optimize existing process flows and develop new innovative solutions to meet product requirements and manufacturability.
• Develop/re-define critical specifications criteria for optimum product performance and drive activities to get them to manufacturing process capability.
• Extract and analyze inline, probe, parametric, reliability, and other critical metrics and predict future behavior of the CMOS device performance of the product to enable early innovative solutions to meet product and device specifications.
• Early introduction, characterization and validation of new CMOS device models and test structures for developing future NAND products.
• 3 dimensions analysis with the use of K2 view to extract layout information and combine with the doping profiles of each implant step for product development and integration solutions.
• Interact and collaborate with TCAD, modeling, and layout teams to drive clearer definition of CMOS device and reliability improvements across multiple tech-nodes and designs.
• Coordinate activities at manufacturing site towards gating experiment funding, conversions, and effectively communicate decisions made to all R&D, manufacturing, and relevant partners.
• Take on leadership role at quarterly yield summits and monthly program reviews in summarizing complex problems, deriving and explaining actions taken to address them and getting R&D, manufacturing, and senior management teams on the same page.
• Assist in the transfer of a new technology from R&D to manufacturing and contribute towards ensuring successful ramp and qualification. Supporting the transfer, documentation and training of module fundamentals into manufacturing.

Requirements:

• MS or PhD in Electrical Engineering preferably specialized in Microelectronics and Semiconductor Device Physics. Prior technology development and tech transfer/manufacturing experiences are preferred.
• Fresh MS/PhD candidates with knowledge of semiconductor process Integration, device physics and CMOS engineering.
• Direct fab experience with nonvolatile memories manufacturing, knowledge of TCAD, K2 view layout, and NAND product are highly desirable.
• Ability to develop a strong, holistic, end-to-end understanding of CMOS device and its related module on NAND technologies, related structural and electrical fail mechanisms.
• Deep understanding of probe failure mechanism, ability to do electrical bench data collection.
• Self-motivated, self-governing with proven ability to work in a demanding and dynamic environment.
• Experienced in coordinating cross-functional teams to achieve a goal.
• Solid data analysis, communication and reporting abilities with demonstrated presentation abilities.
• Curiosity and natural tendency of learning new things independently.
• Ability to travel for extended periods of time to the US for collaborative R&D work.

Working Location: Fab10, 1 North Coast Drive, Singapore 757432

Responsibilities

Excellent execution on assembly process for 1st NPI success and smooth transfer process from NPI to HVM

• Excellent execution of the qualification of NPI products / packages build that proliferate from the pilot products and packages according to planned timeline
• Full responsible on support NPI business process with process TRA, POS, PFMEA/QCP, risk mitigation and documentations.
• Deliver BIC yield and cost on product NPI with integration of DFx BIC package solution, process guideline and design rules.
• Collaboration with multi-functional team from NPI to LVM/HVM process transfer. On-time execution of NPI Customer samples and Engineering Samples build for new products and packages

SME Process Owner Responsible for Continuous Improvement on Process Yield, Defect Elimination and Process Characterization

• Process owner to perform on-time detection with data analysis for process yield improvement. Lead the defect elimination and continue improvement action, with problem solving methodology, statistical analysis and integration solution decision.
• Process owner to develop process recipe for BIC UPH, conducting process characterization to define process parameters and boundary.
• Continuous develop in depth assembly process technical knowledge, well understand process capability/tolerance//spec limit/CpK, and apply key tools PFMEA/QCP/APC/FDC/Alarm on assembly processes Cz/Development/NPI.
• Global leader for cross team collaboration on network BKM, process recipe spec and recipe standardization/conversion.

Technology enablement and development – Process, Material, Equipment

• Participate and support Product Roadmap, to enable key process capability and technology development to ensure packaging solution is ready prior 1st Qual Silicon deliver.
• Frequent engagement with equipment and material supplier (at least interval of monthly or daily/weekly for process issues)
• Collaboration with Supplier and involvement Supplier Roadmap (Material/Equipment/OSAT), to understand market trends and competitor’s direction, ensure key process technology and capability enablement is in-line.
• Frequent review and participant Competitor Analysis, to understand market trends and competitor’s technology/capability boundary
• Engage and follow PDE business process (TGR, TORB, KEG interlock) for new technology qualification, alignment and safe launch

Teamwork and General expectation

• Trainer/Buddy/Mentor for new team members, build effective relationships within team and cross team (peers, counterpart)
• Regularly review data and direction with supervisor. Demonstrate sound data analysis and judgment. Present reports and findings with appropriate conclusions, recommendations and decision making.
• Develop, or coordinate development of, training materials for existing/new process
• Safety Identify and promptly report hazards, follow safety procedures and area work rules including proper PPE, lockout and chemical safety.

Qualification

• Bachelor or Masters in Electrical Engineering, Materials Science, Chemical Engineering, or related field. A PhD is a plus.
• 1-3 or more years of experience in Semiconductor Manufacturing, Process & Equipment Engineering and/or New Product Introduction.
• Demonstrated track record in baseline performance improvement, business process creation, process simulation techniques, data interpretation skills and proficiency in statistical analysis/method.
• Be able to comfortably work across organizational boundaries and geographies.
• Ability to effectively collaborate with multi-functional organizations to understand needs and translate them into actionable plans, deliverables, and resource requirements.
• Organized, meticulous, and strong focus on results.
• Excellent analytical skills
• Excellent communication and written skills

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities
• Install equipment and/or CIP hardware for evaluation by the process development team to enable early introduction, maturity, and adoption for current and next node of 3D NAND technology.
• Work with the Fab layout and facility team to ensure smooth and on time installation and operation of the equipment.
• Work with process development team to quantify benefits of equipment/CIP hardware.
• Develop and optimize existing equipment hardware to meet the productivity requirements of advanced 3D NAND parts.
• Participate with Boise TD equipment development peers on technology choices for the upcoming nodes and able to translate future technology needs into clear equipment requirements.
• Identify disruptive equipment early, work with manufacturing and Boise TD to identify viable evaluation path forward in manufacturing.
• Design and implement advanced equipment monitoring and control methodologies.
• Lead team or sites or suppliers on complex projects in focused meetings with end goal of maturity an equipment technology in record times for technical advantage, cost and productivity.
• Serve as a technical expert within Micron, provide advice and recommendations to senior management on improvements from equipment development. Lead and initiate innovation projects through patents/technical papers.
• Identify and resolve safety hazards; follow safety procedures including lockout, chemical safety, lifting techniques and ergonomically correct methods.

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above
Location: Fab10N
Closing Date: Until filled

As a NAND CMOS Device Engineer, you will help set the direction for current and future CMOS technology for Micron’s NAND Memory Technology Roadmap!

You will work with the Design Team to set electrical targets and define transistor structures to meet these targets. You will guide the device technology development and be in close relation with Process Integration, Design Engineering, Design, Design Rules, Reliability, Transistor Modeling, TCAD (Technology Computer-Aided Design), and Parametric Test, to name a few! In addition, you will ensure that the developed technology is manufacturable and highly yielding and that these considerations are designed into the technology from the start.

Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps

• You give directions on how to improve our device portfolio, both in performance and cost effectiveness
• You define, execute, and analyze silicon experiments for future device generations
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules
• Work with TCAD simulation group to develop strategies for transistor structures to meet targets
• You strive to ensure that transistor models are correctly targeted to anticipate final silicon
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring
• Highly motivated to ensure transistors are developed meeting the required reliability standards
• You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues
• You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues

Minimum Qualifications:

• MS/PhD in Electrical Engineering or related field, PhD in Semiconductor Device Technology preferred
• 5 plus years industry experience in the field of CMOS device design, simulation, characterization
• Experience in developing advanced logic transistor technologies
• Experience in developing Analog FETs operating at higher Voltages
• Preferred: Experience in the field of High Voltage applications, reliability, characterization, device development
• Understanding of analog design concepts
• Good presentation skills
• Excellent team and mentoring skills

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities
• Install equipment and/or CIP hardware for evaluation by the process development team to enable early introduction, maturity, and adoption for current and next node of 3D NAND technology.
• Work with the Fab layout and facility team to ensure smooth and on time installation and operation of the equipment.
• Work with process development team to quantify benefits of equipment/CIP hardware.
• Develop and optimize existing equipment hardware to meet the productivity requirements of advanced 3D NAND parts.
• Participate with Boise TD equipment development peers on technology choices for the upcoming nodes and able to translate future technology needs into clear equipment requirements.
• Identify disruptive equipment early, work with manufacturing and Boise TD to identify viable evaluation path forward in manufacturing.
• Design and implement advanced equipment monitoring and control methodologies.
• Lead team or sites or suppliers on complex projects in focused meetings with end goal of maturity an equipment technology in record times for technical advantage, cost and productivity.
• Serve as a technical expert within Micron, provide advice and recommendations to senior management on improvements from equipment development. Lead and initiate innovation projects through patents/technical papers.
• Identify and resolve safety hazards; follow safety procedures including lockout, chemical safety, lifting techniques and ergonomically correct methods.

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above
Location: Fab10N
Closing Date: Until filled

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities
• Install equipment and/or CIP hardware for evaluation by the process development team to enable early introduction, maturity, and adoption for current and next node of 3D NAND technology.
• Work with the Fab layout and facility team to ensure smooth and on time installation and operation of the equipment.
• Work with process development team to quantify benefits of equipment/CIP hardware.
• Develop and optimize existing equipment hardware to meet the productivity requirements of advanced 3D NAND parts.
• Participate with Boise TD equipment development peers on technology choices for the upcoming nodes and able to translate future technology needs into clear equipment requirements.
• Identify disruptive equipment early, work with manufacturing and Boise TD to identify viable evaluation path forward in manufacturing.
• Design and implement advanced equipment monitoring and control methodologies.
• Lead team or sites or suppliers on complex projects in focused meetings with end goal of maturity an equipment technology in record times for technical advantage, cost and productivity.
• Serve as a technical expert within Micron, provide advice and recommendations to senior management on improvements from equipment development. Lead and initiate innovation projects through patents/technical papers.
• Identify and resolve safety hazards; follow safety procedures including lockout, chemical safety, lifting techniques and ergonomically correct methods.

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above

Location: Fab10N

Closing Date: Until filled

As a NAND CMOS Device Engineer, you will help set the direction for current and future CMOS technology for Micron’s NAND Memory Technology Roadmap!

You will work with the Design Team to set electrical targets and define transistor structures to meet these targets. You will guide the device technology development and be in close relation with Process Integration, Design Engineering, Design, Design Rules, Reliability, Transistor Modeling, TCAD (Technology Computer-Aided Design), and Parametric Test, to name a few! In addition, you will ensure that the developed technology is manufacturable and highly yielding and that these considerations are designed into the technology from the start.

Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps

• You give directions on how to improve our device portfolio, both in performance and cost effectiveness
• You define, execute, and analyze silicon experiments for future device generations
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules
• Work with TCAD simulation group to develop strategies for transistor structures to meet targets
• You strive to ensure that transistor models are correctly targeted to anticipate final silicon
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring
• Highly motivated to ensure transistors are developed meeting the required reliability standards
• You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues
• You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues

Minimum Qualifications:

• MS/PhD in Electrical Engineering or related field, PhD in Semiconductor Device Technology preferred
• 5 plus years industry experience in the field of CMOS device design, simulation, characterization
• Experience in developing advanced logic transistor technologies
• Experience in developing Analog FETs operating at higher Voltages
• Preferred: Experience in the field of High Voltage applications, reliability, characterization, device development
• Understanding of analog design concepts
• Good presentation skills
• Excellent team and mentoring skills

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

Advance Packaging Integration – Senior Engineer (Package Development Engineering, Silicon Technology Package Integration) (PDE STPI)

We are looking for a Package Silicon Integrator in Package Development Engineering (PDE) Senior Engineer who will lead and drive Micron’s Packaging Technology Development Projects meeting Time to Market (TTM) business unit needs as well as meeting performance targets for Thermal, Electrical, Mechanical, Reliability and Cost. You will collaborate with Micron’s multi-functional team that include Product Development, Wafer level process, Assembly, Test, Manufacturing and Global Quality. Together, we will be responsible for the designing Test Vehicle Development Strategy, and execution to definition, development, and delivery of state-of-the-art product/packages that will shape the future of advanced computing, automotive and mobile products.

Responsibilities will include, but are not limited to:

• Drive package technology integration activities for the silicon test chip development projects and support NPIs to keep roadmap items on track to meet “go to market” timelines.
• Coordinate core team in Development and NPI space of advanced 2.5D/3D packages and standard packaging to drive material and BOM choices, body sizes, manufacturability, and package constructions to achieve acceptable Design for Manufacturing (DFM) and Design for Reliability (DFR) requirements.
• Evaluate wafer design inclusive of bondpad, scribe, pillars/bump and polyimide, and drive materials and BOM choices such as die thickness and mold compound to meet chip package interaction requirements.
• Drive materials characterization from both package and die components to understand chip package interaction mechanism using TMA, DMA, nanoindentation, and packaging mechanical and thermal stress stimulus.
• Drive novel solutions with silicon design and product teams to recommend the optimum package solutions to meet electrical, mechanical (1st, 2nd, and 3rd level interconnect), thermal, reliability, cost, and other system level requirements.
• Interface closely with multi-functional team that include Product Development, Wafer Level Process, Assembly, Test, Manufacturing and Global Quality and manage the product/package to mass production.

Requirements:

• Bachelor/Masters of Science in physics, materials, mechanical, chemical, or electrical engineering. MS or PhD preferred
• 5+ years of relevant experience in semiconductor manufacturing or a related field, with hands-on experience in semiconductor packaging or Frontend processes, specifically in technology on
• Appreciation for Structured Problem Solving
• Ability to interpret die-, package-, and system-level design and simulation (thermal/mechanical/electrical) methodologies and results
• Knowledge in Chip Package Interaction (CPI)
• Experience and working knowledge with 2.5D/3D heterogeneous integration technologies such as WLFO, SoIC, CoWoS, WoW, InFO, and other chiplet/SiP architectures is a plus
• Experience with wafer bumping, package assembly, substrate technology, BOM selection, testing and product development lifecycle
• Excellent communication skills with the ability to convey complex technical concepts to both technical and non-technical partners
• Demonstrated leadership experience in guiding multi-functional teams and driving technical excellence

Keen on the role? Apply now!

Advance Packaging Integration – Senior Engineer (Package Development Engineering, Silicon Technology Package Integration) (PDE STPI)

We are looking for a Package Silicon Integrator in Package Development Engineering (PDE) Senior Engineer who will lead and drive Micron’s Packaging Technology Development Projects meeting Time to Market (TTM) business unit needs as well as meeting performance targets for Thermal, Electrical, Mechanical, Reliability and Cost. You will collaborate with Micron’s multi-functional team that include Product Development, Wafer level process, Assembly, Test, Manufacturing and Global Quality. Together, we will be responsible for the designing Test Vehicle Development Strategy, and execution to definition, development, and delivery of state-of-the-art product/packages that will shape the future of advanced computing, automotive and mobile products.

Responsibilities will include, but are not limited to:

• Drive package technology integration activities for the silicon test chip development projects and support NPIs to keep roadmap items on track to meet “go to market” timelines.
• Coordinate core team in Development and NPI space of advanced 2.5D/3D packages and standard packaging to drive material and BOM choices, body sizes, manufacturability, and package constructions to achieve acceptable Design for Manufacturing (DFM) and Design for Reliability (DFR) requirements.
• Evaluate wafer design inclusive of bondpad, scribe, pillars/bump and polyimide, and drive materials and BOM choices such as die thickness and mold compound to meet chip package interaction requirements.
• Drive materials characterization from both package and die components to understand chip package interaction mechanism using TMA, DMA, nanoindentation, and packaging mechanical and thermal stress stimulus.
• Drive novel solutions with silicon design and product teams to recommend the optimum package solutions to meet electrical, mechanical (1st, 2nd, and 3rd level interconnect), thermal, reliability, cost, and other system level requirements.
• Interface closely with multi-functional team that include Product Development, Wafer Level Process, Assembly, Test, Manufacturing and Global Quality and manage the product/package to mass production.

Requirements:

• Bachelor/Masters of Science in physics, materials, mechanical, chemical, or electrical engineering. MS or PhD preferred
• 5+ years of relevant experience in semiconductor manufacturing or a related field, with hands-on experience in semiconductor packaging or Frontend processes, specifically in technology on
• Appreciation for Structured Problem Solving
• Ability to interpret die-, package-, and system-level design and simulation (thermal/mechanical/electrical) methodologies and results
• Knowledge in Chip Package Interaction (CPI)
• Experience and working knowledge with 2.5D/3D heterogeneous integration technologies such as WLFO, SoIC, CoWoS, WoW, InFO, and other chiplet/SiP architectures is a plus
• Experience with wafer bumping, package assembly, substrate technology, BOM selection, testing and product development lifecycle
• Excellent communication skills with the ability to convey complex technical concepts to both technical and non-technical partners
• Demonstrated leadership experience in guiding multi-functional teams and driving technical excellence

Keen on the role? Apply now!

As Facilities Utilities Engineer of Global Construction team, you will be an integral member of the Global Facilities Line Planning Group responsible for overseeing and managing the analytical duties related to facility utilities planning program, assisting in the planning and design of facilities construction and expansion projects. You will be responsible for managing Micron Facility utilities consumption assessment process, analyzing facility future needs and resource utilization analysis.

In this role, you manage utilities related projects, programs and will help to plan and prioritize resources needed to achieve results and assure accurate tracking of projects and programs to predict results and outcomes critical to success.

Responsibilities

• Collect, classify, evaluate utilities data and information used in supporting the facilities utilities consumption management and capital program.
• Create reports, charts, graphs and eventual monitoring system for Facilities Services.
• Define, manage and improve on Micron Tools Utility Matrix (TUM) Business Process.
• Drive network alignment among Micron sites in tools utility matrix (TUM) database.
• Drive network alignment across sites in Tools’ process independent utilities database and eventually moving towards alignment for Tools’ process dependent utilities database.
• Work closely with Teams from Global and Site Facilities, Global Planning, Facilities Transfer Team, CPEE & IEs to coordinate and drive facility utilities estimates for new layout, technode scenarios.
• report program status, wins, issues, and actions to program sponsor for broadcasting to global leadership team and stakeholders
• Ensure Roles, Responsibilities and Accountabilities are fully understood by the participated teams

Skills / Qualifications

Minimum Qualifications:

• The candidate should possess a BSc or Beng in Engineering from a recognized institute of higher learning.
• Experience in wafer fab facilities systems is highly valued.
• Candidates with experience in facilities operation & construction.
• Minimum 3 years of Facility or Equipment tool Management experience in Semiconductor manufacturing environment
• Demonstrable experience in the Facility or Equipment tool utilities Management and/or other relevant industries is strongly preferred.

As Environment, Health and Safety (EHS) senior engineer, you will be responsible for the implementation of Fab10’s EHS programs at the site. You will conduct/coordinate EHS training to employees, conduct periodic EHS audits and surveys to identify level of implementation and efficiency of EHS management system, identify potential gaps or improvement opportunities and recommend measures and improvement plan to management. You will also be liaising with external organizations on EHS compliance issues.

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities and Tasks

• Ensure Micron's safety programs and procedures are effective, efficient, and conform to the Management System and regulatory requirements
• Develop and implements functional, cost-effective solutions for safety issues
• Coordinates, manages, and conducts safety walks, inspections, and audits to ensure operations comply with Micron safety procedure and regulatory requirements
• Responds to emergencies and investigates incidents and recommends preventive/corrective action
• Collect, analyze, and communicate safety related metrics and performance measurements.
• Support ISO System by participating in internal audits to continuously improve our safety program and procedures.
• Identify, develop, and provide safety training in accordance with company goals and objectives,

Education & Qualifications

• Bachelor's degree in occupational health and safety or related filed e.g. Engineering
• Safety and Health Certifications eg. Certified Safety Professional, WSH Safety Officer Certification, ISO auditor training and certification
• Experience with ISO 45001:2018 Occupational Health and Safety Management System
• Ability to read and develop understanding and interpretation of safety regulations
• Strong interpersonal communication and collaboration Department
• Minimum 4 years + of experience in related field

Develops, implements and monitors company safety programs and policies. Ensures compliance with government health and safety regulations. Conducts employee training in emergency response, life safety, industrial hygiene, and chemical and fire hazards. Conducts safety surveys and recommends corrective action where occupational hazards exist. Responds to emergencies and investigates accidents and recommends corrective action. Completes required federal, state and local government reports relating to safety.