Total 175 purchasing engineer job vacancies in D27 Yishun, Sembawang

You are responsible for, but are not limited to, the following:

• Develop and optimize unit processes to meet the yield and quality requirements of advanced Replacement Gate 3D NAND parts
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement
• Prioritize within Singapore based manufacturing Dry Etch team on the key technology issues that need R&D breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement
• Participate with Boise R&D peers on technology choices for the upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Identify process simplification opportunities and drive multi-functional teams in implementation
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Provide advice and counsel to management on significant technical issues. Lead and initiate ground breaking projects through patents/technical papers.
• Communicate and collaborate with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a requirement.
• Be part of the continuous worldwide R&D engagement with suppliers pushing for breakthrough solutions.

You should possess

• Masters/PhD in Electrical & Electronics, Chemical, Mechanical, Materials Engineering.
• Strong aptitude for research and development and ability to create production-worthy technologies.
• Ability to develop and maintain relations with multi-functional teams and vendors.
• Strong communication skills (written, verbal and presentation).
• Highly motivated and adaptable to our demanding, dynamic and rapidly changing work environment; flexibility to work for extended hours, as required.
• Ability to travel to US R&D site for few months to engage in collaborative R&D work.

As an EUV Photo Project Engineer in Operation Central Team (OCT) Central Process and Equipment Engineering (CPEE) Photo Scanner at Micron Technology, Inc., you will lead project activities to achieve and maintain outstanding EUV Ecosystem in high volume manufacturing.

You will be responsible for providing leadership to the global Micron network to drive Photo EUV Productivity, Hardware, Application, Value Engineering, Continuous Improvement Program, Cost reduction, TOR and BKM governance through technical expertise, business process management and project execution.
You'll be working closely with various teams like Process Equipment Engineering Groups, Technology Development, Procurement, and the Central Team, as well as interacting with equipment suppliers to address manufacturing issues. Effective collaboration with manufacturing sites, Quality Engineering, and other functional departments is key, with an exciting element of international travel to achieve your goals.
It’s a great opportunity for someone who enjoys challenges in State of Art Technology in EUV, teamwork and global experiences!

Responsibilities:

• Ensure a safety-first culture for all program and project solutions.
• Oversee the EUV Litho Cluster, including Scanner and Track installation, to meet TIQ (Tool Installation Qualification) goals.
• Close collaboration with EUV ecosystem suppliers (ASML, TEL, Edward Zenith, Zinter, etc) and internal partners (HVM fabs, Central Teams, Technology Development teams).
• Manage EUV Reticle support tools (e.g., Reticle inspection tools, Reticle Clean tools, EUV Reticle pod storage, Pod Clean tools etc) through closed collaboration with Fab and Central Reticle Teams.
• Drive EUV Industrialization goals by leading Supplier Workstream Programs (Eg: Scanner, Source, Drive Laser, TEL Track etc) to achieve industry outstanding performance in Imaging, Overlay, Rework, Defectivity, and Efficiency (Wafers Per Day).
• Drive and facilitate Governance meetings and cross-collaboration projects with internal and external partners to achieve Micron Strategic Initiatives (Eg: cost, yield, quality, Maxout, environmental sustainability).
• Demonstrate strong communication and reporting skills to provide regular Executive updates on project progress, challenges, and escalation for resource support.
• Oversee processes, guide initiatives, and lead project team members toward goal achievement using analytical skills and problem-solving techniques.
• Proactively identify bottlenecks, drive improvements, and share standard methodologies across HVM fabs.
• Demonstrate ownership and accountability in delivering results.

Requirements:

• Global Factory Network Expertise: Demonstrated understanding of worldwide high-volume manufacturing network operations across different geographical region.
• Leadership and Strategic Initiatives: Proven ability in team development and leading transformative initiatives.
• Manufacturing Knowledge: Familiarity with Front End (FE) manufacturing, reticle manufacturing, and fab processes.
• Project/Resource Management: Ability to manage Global Project and Resource.
• Effective Communication: Skilled at communicating effectively across various organizational levels.
• Customer-Focused Project Management: Proficient in project management with a strong customer focus.
• Continuous Learning Advocate: Continuous learning on the job and provide technical mentoring for peers.
• Minimum 4 years’ experience working as Photolithography Equipment/ Process Engineer or Photo Scanner Engineer in Wafer Fab. ASML EUV Scanner experience will be an advantage
• Bachelors/master’s degree in Electrical, Electronics, Mechanical Engineering

You will be responsible for providing leadership to the global Micron network to drive Photo EUV Productivity, Hardware, Application, Value Engineering, Continuous Improvement Program, Cost reduction, TOR and BKM governance through technical expertise, business process management and project execution.
You'll be working closely with various teams like Process Equipment Engineering Groups, Technology Development, Procurement, and the Central Team, as well as interacting with equipment suppliers to address manufacturing issues. Effective collaboration with manufacturing sites, Quality Engineering, and other functional departments is key, with an exciting element of international travel to achieve your goals.
It’s a great opportunity for someone who enjoys challenges in State of Art Technology in EUV, teamwork and global experiences!

This is an exciting and fast-paced position! Our team Application Development & Support(ADS) delivers software solutions to leadership and engineers throughout Micron's global manufacturing network. As Operations Central Team (OCT) Software Development Engineer at Micron Technology, Inc., we have the chance to create and improve Micron systems and processes on a global scale.

Collaborate with customers across departments and geographical sites to design, develop, innovate and support software throughout the development life cycle. Be part of the team to support efficient business processes by maintaining a focus on global alignment, and participating in efforts to research and influence technology roadmaps.

Responsibilities:

• Demonstrate Micron core values People, Innovation, Tenacity, Collaboration, and Customer Focus
• Gather requirements by working closely with customers
• Design, develop, debug, document, test, and deploy applications
• Collaborating with other developers on the team
• Working closely with Business Operation Teams, Product and Application Development teams, and other internal customers during application development and deployment
• Provides 24x7 Support

Project Description

• Join an agile team to develop a web solution for Micron globally, including but not limited to API, ETL, and database projects.
• Work on new or existing projects.

Learning Outcomes

• Gain hands-on development experience in modern tools and pioneering tech stacks (Angular, OpenShift, Azure)
• Learn to work effectively in the Agile development team to develop successful product with timely delivery
• Gain domain knowledge on semiconductor industry
• Develop problem-solving and analytical skills and good software engineering practices
• Enhance communications, interpersonal, and other critical skills in the professional environments

Qualifications and Traits

• Proficient in Angular, .NET Core, C#, and SQL.
• Knowledge of containerized deployment with Docker, Kubernetes, and OpenShift is a plus.
• Strong analytical, problem-solving, and interpersonal skills.
• Motivated to work in a dynamic and fast-paced environment.
• Ambitious and driven to complete tasks independently while recognizing ways to improve processes.
• Active team participation, partnership, and consensus-building skills.
• Good verbal and written communication skills.

Education Required

Bachelors Degree or equivalent experience in Computer Science or related field of study

Experience Required

2 years of experience in 3 or more of the following:

• Experience in front-end web development (preferably Angular, ASP.NET)
• Proficiency in C# and Object Oriented Programming
• Proficiency in HTML, CSS, JavaScript
• Experience in RESTful Web API development (preferably ASP.NET Core, Node.js)
• Experience with Agile development methodologies
• Good understanding of one or more database technologies (MSSQL, ORACLE, Snowflake, MongoDB, CouchDB)
• Experience in SSIS, SSRS, Tableau, PowerBI or any Business Intelligence technologies Bonus if you have experience in Python and cloud programming, CICD (Azure), NiFi
• Knowledge of source code repositories (Git)
• Knowledge of SQA is a bonus

Responsibilities

• Develop and optimize unit processes to meet the yield and quality requirements of advanced NAND part type
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement Prioritize within Singapore based manufacturing Wet Etch team on the key technology issues that need TD breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement Participate with Boise TD peers on technology choices for the upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work with manufacturing and Boise TD to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Initiate and manage experiments to widen process margins as well as to test out manufacturability of next node solutions
• Identify process simplification opportunities and drive cross functional teams in implementation Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Serve as a technical expert within Micron contributing to technical projects for improvements to processes, procedures and equipment.
• Lead team or sites or suppliers on complex, multi-disciplinary projects in quality focused meetings, process and yield improvement meetings, cost and productivity improvement meetings
• Provide advice and counsel to management on significant technical issues. Leads and initiate innovation projects through patents/technical papers.
• This position requires communications and collaboration with partners both locally and globally.
• Strict adherence to Micron Intellectual Property protection policy is a must.

Be part of the continuous worldwide TD engagement with suppliers pushing for breakthrough solutions.

Requirements

• Masters/PhD graduates in Materials Science, Chemical/Microelectronic Engineering or Chemistry are welcomed to apply.
• A deep understanding of chemistry, chemical kinetics, thermodynamics and mass transport
• 2-3 years of experience in Semiconductor Equipment/Process development is preferable
• An understanding of the general process steps and process flow for memory processing, planar and vertical NAND memory in particular.
• Working knowledge of data analysis systems e.g.: Y3 to facilitate analysis of experimental data
• Working knowledge of Design of Experiments (DoE) Proven ability to collaborate with local and overseas teams on projects
• Excellent oral and written communication skills with ability to convey the message in concise and effective manner both in local as well as remote communications.
• Ability to be a self-motivated individual and be adaptable to Micron’s changing needs in terms of working extended hours, if required Proven ability to work in a demanding & dynamic environment and able to prioritize and manage multiple projects simultaneously
• Ability to travel for extended periods of time and stay at Boise TD for 2-4 months at a stretch to work on technology development.

As the Facilities SmartFac & Control Engineer, you are required to lead engineering and maintenance works in the fields of SMART Fac and Control systems on site, with the necessary guidance and direction from Facilities organization, to achieve facilities department, site, facilities corporate and company goals.

• Lead on site Smart System transformation and on implementation of Smart FAC projects with AI-enabled detection and analytics in collaboration with other Micron Departments.
• Lead on Sustainability and Environmental Control system deployment with early detection and predictions, using Industry 4.0 system.
• Lead on labor productivity automation projects with innovative idea to improve facilities team efficiency.
• Plan, design and lead Control Automation engineering projects includes new construction, system upgrading and quality improvement.
• Lead troubleshooting and attend to abnormalities in support of Operations in a timely manner on system under Smart FAC & Control section when required.
• Lead on the planning and supervise Preventive and Corrective Maintenance work activities, priorities and reallocate resource when required.
• Perform capacity tracking and planning for Instrumentation and Control systems.
• Acquire estimated cost and raise purchase requisition for service or parts necessary for repair and maintenance purpose, when required.
• Utilize computer base software to document and analyze records of work order and equipment history.

Job Requirements:

• Bachelor Degree in Electrical/Electronics/Computer engineering or equivalent related field.
• Good knowledge on Python, Java, C/C++, C#, SQL, machine learning.
• Good knowledge in programming of programmable logic controller (PLC) and process automation PID control.
• Good knowledge of various handheld tool, portable and panel measuring device and equipment.
• Ability to understand and use schematic, single-line drawing and related equipment and system documentation
• Ability to work in a team environment with various professional level.

Your responsibilities will include, but are not limited to

• Manage network tool utilizations strategies and benchmark performance to optimize the company’s deployed capital
• Manage and communicate improvement and implementation plan to all relevant levels and functions in Manufacturing
• Optimize capacity of install equipment and lead sites and tool level optimization studies for throughput enhancement
• Collaborate with partners to understand future tool and process roadmaps. Able to assess network capacity impacts of process changes
• Improve financial analyses before capital equipment are purchased through automating metrics optimizations, process flexibility, capacity sharing and equipment repurpose
• Attention to detail and ability to work in situations where changes is fluid
• Ability to spot, question and highlight differences to drive resolutions with relevant stakeholders

Requirements :

• Bachelors’ Degree in Engineering, Computer Science, or a Business-related or quantitative field (Finance, Economics or similar discipline). MBA or Master’s degree is a plus
• Experience turning complex and ambiguous problem statements into structured solution while working in a highly multi-functional environment
• Experience operating independently while maintaining a high degree of organization, control and change management
• Experience analyzing and interpreting data, drawing conclusions, defining recommended actions, and reporting results cross diverse technical and non-technical groups
• Experience working in teams, establishing and maintaining multi-functional relationships
• Experience in a combination of capacity analysis, business analysis or process analysis is advantageous

Work Location

• F16 Taichung, Taiwan
• F15, Hiroshima, Japan
• F10A, Singapore

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

This position focuses on strategy and modeling creation, improving global standardizations, enable sustainability through automation, synchronizing the processes and scaling the solutions to transform the inline interdiction and operation system automation for RAM Quality and Operation Engineering sections.

Responsibilities:

• Establish and improve BKM (Best Known Method) for RAM quality defense line, sampling methodology, sampling systems and operation efficiency.
• Improve quality and yield performance by reducing defect OOC% variation.
• Keen to learn new skills, initiate proactive and continuous improvement projects, in areas across the Front-End including manufacturing methods and processes, quality, software systems, cycle time, key tool metrics (utilization, and performance efficiency), maintenance and routine tasks, and other manufacturing support operation.
• Establish metrics that can efficiently audit adoption rate and compliance to business process, BKM and strategy and perform audits.
• Perform quality deviation investigations, fab metrics benchmarking analysis and find opportunity for improvements.
• Lead and facilitate discussion to drive network alignment on strategy business process and roadmap to achieve area objectives and deliver to timelines/commitments. Ensure BKM sharing spans across all sites regardless of technology and/or site mission differences.
• Actively provide recommendations to improve and optimize programs and processes to the respective program and/or process owners.
• Provide tactical support and coordination for the Fabs for issues of People, Safety, Yield, Quality, Cost, and Cycle Time when required.

Qualifications & Skills:

• Good communication skill, maintain a strong and open relationship with peer group and appropriate team members in other functional areas such as Process Integration Engineering, Quality Systems, Production Operations Management and present strategy and updates to network members and leaders.
• Proficient in project management with good resource planning, status monitoring and deliver timely results.
• Promote worldwide sharing and transfer of area-specific knowledge.
• Proficiency, experience, and knowledge relating to product and test wafer capacity modeling, wafer at risk modeling, Failure Mode Effect Analysis (FMEA) concept and system, defect analysis tools, sampling strategy and systems, Statistical Process Control (SPC) tools, Cycle Time Management, tableau creation, SQL and Programming language and Organizational Change have advantage.

Education and Experience:

• Masters/bachelor’s in engineering
• Relevant working experiences in RDA and/or Metrology
• Willing and capable of international travel, including Extended International Business Travel (EIBT) assignment to 6 months as needed, to accomplish the goals.

Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.

We are looking for a highly motivated, ambitious, result driven individual with strong work ethic and integrity to join us as a Photolithography Process Development Engineer/Senior Engineer in NAND Technology Integration (NTI) R&D group. You will be using state of the art equipment to support activities associated with rapid deployment of technology nodes, process margin improvement activities and ensure extended engagement with manufacturing on the upcoming technology nodes.

You are responsible for, but are not limited to, the following:

• Develop and optimize lithography processes to meet yield and quality requirements of advanced Replacement Gate 3D NAND parts
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement
• Prioritize within Singapore based manufacturing photolithography team on the key technology issues that need R&D breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement
• Collaborate with Boise R&D peers on technology adaptation and cost optimization towards upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Identify process simplification opportunities and drive multi-functional teams in implementation
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Provide advice and counsel to management on significant technical issues. Lead and initiate ground breaking projects through patents/technical papers.
• Communicate and collaborate with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a requirement.
• Be part of the continuous worldwide R&D engagement with suppliers pushing for breakthrough.

You should possess

• Masters/PhD in Electrical & Electronics, Chemical, Mechanical, Materials Engineering.
• Strong aptitude for research and development and ability to create production-worthy technologies.
• Ability to develop and maintain relations with multi-functional teams and vendors.
• Strong communication skills (written, verbal and presentation).
• Highly motivated and adaptable to demanding, dynamic and rapidly changing work environment; flexibility to work for extended hours, as required.
• Ability to travel to US R&D site for few months to engage in collaborative R&D work.

Possess the above qualities ? Join Us !

Responsibilities:

• Review and analyze experimental process flows: Identify defect anomalies and quarantine out-of-control process tools.
• Embrace continuous improvement: Seek ways to enhance operations
• Raise awareness of process anomalies: Recognize and communicate issues promptly.
• Leverage inline process signals: Drive process improvements using real-time data.
• Explore new inspection tools and strategies: Aim for earlier problem detection and source identification.
• Innovate with existing tools: Develop techniques to identify relevant process issues.
• Manage image classification models: Enable automated reporting systems.
• Collaborate with the global network to develop best-known methods and maintain alignment between sites.

Requirements:

• Bachelor’s/ Masters in Engineering would be advantageous
• Experience with semiconductor inspection equipment is preferred.
• Data Science and Data Manipulation skills: Ready to learn and apply basic scripting, coding, or programming.
• Preference for metrology or inspection experience: Especially related to data analysis and root cause investigation.
• Capable of international travel up to 3-5 months
• Good communication skills (verbal and written)

Job Responsibilities

• Advanced process development tasks SEM CD, OCD or other metrology techniques in 3D NAND technology.
• Identify and provide solutions for inline detection in collaboration with process engineer and process integration.
• Identify modeling opportunities using metrology and detection data to explain electrical failed signature at probe
• Collaborate with US TD Metro team on technology choices for the upcoming nodes and able to translate future technology device needs into clear equipment roadmap requirements.
• Work closely with the planning team to understand Model-on-record (MOR) impact of new technology. Maintain MOR accuracy to enable successful technology ramp.
• Influence vendor equipment roadmap to enable new technology development in Micron

Requirements:

• Bachelor’s/ Masters in Engineering would be advantageous
• Experience with semiconductor inspection equipment is preferred.
• Data Science and Data Manipulation skills: Ready to learn and apply basic scripting, coding, or programming.
• Preference for metrology or inspection experience: Especially related to data analysis and root cause investigation.
• Good communication skills (verbal and written)

As NAND Sg Process Development (PD) Program Management Engineer, you will support the Program Manager, in his collaboration work with Technology Development (TD) peers, High Volume Manufacturing (HVM) Fabs, Operations Central Teams (OCT) and other stakeholders to drive best in class performances and all critical initiatives for NAND nodes to meet program milestones.

You will play a key role in establishing and managing cost programs to meet allocated capital expenditure budget, operational expenditure cost management; and deliver node-over-node cost per gigabit (CPGB) reduction targets meeting business requirements.

You will work in a fast-paced environment with the world’s Best NAND TD team in a role that is highly Collaborative and requires a great deal of Customer Focus; continuous improvement and an Innovative growth mindset are required to achieve desired results. You will work within a Process Development organization alongside leaders and engineers from Fab functional Process Areas.

Responsibilities:

• Regular interaction with PD/PI team for MOR Updates/Tracking in close collaboration with Industrial Engineering (IE) Modeling Team.
• Drive alignment and timely delivery of results on critical projects, manage execution of TD roadmaps/strategies to meet milestones.
• Drive continuous improvement of PMI/SPC from process areas, publish roadmaps, highlight risks and mitigate.
• Prequal Expense: Work with stakeholders to drive prequal expense reduction (materials, spares etc).
• TD-University Engagements: Engage with Talent Acquisition teams to initiate/support initiatives to build strong TD talent pipelines.
• EBD Grants: Collaborate with Finance Team to comply with regular submissions and meet yearly audits.
• Additional portfolio includes Micron Voice Engagements, managing Dept budget, compliance with NMI processes, related TD audits and new scopes along the way that contribute to NAND program successes.

Successful candidates for this position will have:

• Bachelor/Masters in related Engineering fields.
• Familiar with both TD and manufacturing environment and business processes
• Extremely strong organizational and communication skills.
• Strong interpersonal skills for smooth collaboration with cross-functional teams.
• Solid communication skills for cross department alignment and providing clarity to leadership and executive teams.
• Highly motivated and adaptable to our demanding, dynamic and rapidly changing work environment.

Responsibilities :

Equipment Performance

• Come up with methodologies to improve %UD/SD performance globally.
• Design Tier 2/3 matrices to improve %UD/SD.
• Develop suitable global reports for sites to benchmark against each other on %UD/SD
• Design and implement a process to improve workstations MOR %UTIL through %MA & Lost time improvement.
• Study the wafer path taken in critical workstations.
• Identify key data that needs to be extracted from the tool EDA system to map the time taken to complete wafer processing.
• Collaborate with SMAI to build a system to compare the wafer processing time between tools within a workstation.
• Quantify capex avoidance/savings that arise from improving Equipment Performance.

Address Tool to Tool mismatches in Process Areas

• Build a database of inputs for all process areas to address tool to tool mismatch proactively.
• Database of inputs should cover the cross matching of software, hardware & process related inputs.
• Collaborate with SMAI to build a system using these inputs to identify & fix tool to tool mismatches in a workstation.
• Appropriate measures, processes, and metrics should be devised to handle and maintain tool to tool mismatches effectively.

Standardization of practices & BKMs in Process Areas

• Setup global area alignment teams to address chronic issues, drive improvements & eliminate wastes.
• Channel improvements and lessons learnt established from various forums, eg. TPM Forum, Excursion Review, etc.  into global area forums to decide on the standards for deployment, implementation and audit.
• Design suitable matrices for each process area so that improvements impact the 4 pillars.
• Create a library of area level BKMs for Equipment & Process Engineers to search for standards involving the setup of Equipment & associated processes.
• This library must also serve the purpose to feed-forward area level BKMs to TD for process development & HVM for improvement work that will impact the 4 pillars.
• Sit in transfer reviews to ensure N-1 standards are fed-forward to N technode for sustenance

Demonstrate Leadership

• Adopt benchmarking and deliver strategies to close the gaps.
• Challenge complacency and do not let strong market conditions give a false sense of reality.
• Gain insights into the competitor's culture, approach, and capabilities.
• Understand that the only way to guarantee our future is to be the best.
• Understand the challenges your team faces.
• Don’t underestimate the effort it takes to be number one.
• Ignite the passion in people to achieve the impossible.
• Dare to set high targets, expect innovation and breakthroughs.
• Give honest, tough, but productive feedback to the team, and be willing to receive it yourself.
• Challenge others and be willing to stand for something.
• Have the courage to turn a crisis into an opportunity.
• Lead from the front and lead by example.
• Become the team that will out-innovate and out-execute the competition. Don’t accept anything less.
• Be unrelenting and “unreasonable”.
• Cultivate a habit of winning. Winning breed’s confidence.
• Find top talent willing to take risk and support them in doing the exceptional.
• Face unsolvable problems head-on and turn them into opportunities.
• Develop teams and team members to enable them to reach their full potential and reward them accordingly.
• Support team members with coaches and mentors who push TM outside their comfort zone.
• Lead the team to success.
• Leave a legacy behind that we are proud of.
• Believe in your team.

Requirements :

• Bachelors Degree in Electrical / Electronics / Semiconductor Engineering
• 10 years of experience and/or demonstrated ability in any of the following Field (Equipment or/& Process)
• Preferably experienced in Photo & PCVD area.
• Applicants must have a consistent record to collaborate globally and influence by indirect leadership in order to drive resourcing to critical projects across Micron.
• Applicants must have a shown capability in dealing with complexity and an ability to apply resources effectively to bring clarity to required actions.
• Applicants must hold a record of performance excellence for current area of responsibility; and are recognized as having demonstrated successful leadership characteristics both in present and past jobs.
• Applicants are viewed by current reports as an excellent mentor, team builder and motivator.
• Applicants must have demonstrated the ability to solve problems across multi-functional groups, both within and outside their department/Site.
• Applicants must have experience handling large, multi-layer groups that encompass a variety of fields.
• Applicants must have proficiency in handling through systems, informing, organizational agility, dealing with ambiguity, and listening. They must demonstrate a strong alignment with Micron Behaviors and the skills they'll use every day.

As a Senior- level Device Engineer in Micron's Front End Central Process Integration Engineering (cPIE) team, you will co-work with the global Micron network on improving Device performance to meet product yield and quality requirements, through optimizing process steps, reducing device variability, optimizing design layout or test specs, and standardizing device engineering business process and working methodology. The primary focus could be either DRAM or NAND flash memory when needed.

Requirements:

• Bachelor's degree with a minimum 5 years of relevant working experience is required. Master's or Ph.D. degree in Physics or Engineering areas is preferred.
• Working experience in fab process or process integration or test engineering. Direct experience in CMOS or NAND/DRAM memory device engineering is preferable.
• Require proven knowledge in semiconductor physics and understanding of transistor operations, scaling limitations and reliability, basic knowledge of CMOS circuits and characterization methods. Experience in advance transistor architectures such as High-K metal gate or FinFET or GAA is preferred.
• Deep understanding of at least one semiconductor fabrication process area, including tool sets, process mechanism, tuning knobs, etc.
• Excellent data analysis skills using at least one software (JMP, SPOTFIRE, etc).
• Strong task ownership, self-motivated to work with other team members to make progress collaboratively.
• Open-minded attitude to learn new skills and could adapt to new working environment swiftly.
• Good communication skills. Proficient in English (speaking and written). Working-level communication capability in Mandarin Chinese OR Japanese is preferred.
• Good digital literacy with MS office. Programming capability such as Python is a plus.
• Occasional domestic and international business travel is required.

Job responsibility:

cPIE Device Engineer, responsible for product yield and quality improvement, by working collaboratively with Micron global network, to improve device performance, standardize business procedure and working methodology.

Your primary responsibilities will be:

• Risk assessment of NAND cell reliability, identification of the process/trim/test strategy to bridge the gaps for JEDEC and internal product qualification.
• Design experiments to identify and segment the limiting reliability mechanisms impacting NAND quality.
• Design high volume electrical experiments (both wafer level and component level) and perform statistical data analysis to validate process/trims solutions required to close reliability gaps.
• Update management and provide continuous feedback to process development and product engineers on the NAND reliability status and roadmap to bridge gaps.
• Contribute to develop forward looking technology path finding for next NAND generation, including reliability risk assessment and product capability projections, identify innovative design and product features required to meet quality specification.

Required skills:

• Proven experience with NAND device structures, operations and algorithms
• Knowledge and understanding of electrical properties of semiconductor and insulator materials, semiconductor device physics and solid-state physics
• In-depth understanding of physics-based modeling of non-volatile memory and semiconductor devices failure mechanisms, reliability analysis
• Knowledge and understanding of statistical analysis and numerical computing software (Matlab, Octave, JMP)
• Knowledge and ability of scripting languages (C, C++, Matlab, Perl)
• Familiar with Big Data and database queries
• Knowledge of JEDEC standards

Your primary responsibilities will be:

• Risk assessment of NAND cell reliability, identification of the process/trim/test strategy to bridge the gaps for JEDEC and internal product qualification.
• Design experiments to identify and segment the limiting reliability mechanisms impacting NAND quality.
• Design high volume electrical experiments (both wafer level and component level) and perform statistical data analysis to validate process/trims solutions required to close reliability gaps.
• Update management and provide continuous feedback to process development and product engineers on the NAND reliability status and roadmap to bridge gaps.
• Contribute to develop forward looking technology path finding for next NAND generation, including reliability risk assessment and product capability projections, identify innovative design and product features required to meet quality specification.

Required skills:

• Proven experience with NAND device structures, operations and algorithms
• Knowledge and understanding of electrical properties of semiconductor and insulator materials, semiconductor device physics and solid-state physics
• In-depth understanding of physics-based modeling of non-volatile memory and semiconductor devices failure mechanisms, reliability analysis
• Knowledge and understanding of statistical analysis and numerical computing software (Matlab, Octave, JMP)
• Knowledge and ability of scripting languages (C, C++, Matlab, Perl)
• Familiar with Big Data and database queries
• Knowledge of JEDEC standards

Working location:

• 1, North Coast Drive, Singapore 757432

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

FE Central Product Integration Engineering (CPIE) HPM PI Engineer

As FE CPIE HPM (High Performance Memory) PI Engineer at Micron Technology, Inc., you will be responsible for working with global Micron network to drive HPM Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution.

Responsibilities and Tasks

• Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering.
• Active engagement with PI Loop taskforce and/or team in network to address yield and quality challenges, optimize process flow in a timely manner to achieve BIC yield performance.
• Maintain and enhance domain knowledge and technical expertise, explore innovation opportunities with strategic thinking and systematic approach.
• Maintain a strong and open relationship with peer group and managers in other functional areas within central team and outside in areas such as Fab, TD, Product Engineering, GQ. Communicate and respond to issues in a timely manner. Help drive to fix the issue where necessary.
• Demonstrate ability to give effective presentations to both small and large groups on project updates and new initiative proposals.
• Periodically follow up with manager to ensure all type of goals are met and get assistance to remove obstacles.
• Travel to Micron Fab locations as necessary for face-to-face collaboration for program requirements.

Requirements

• Background in electrical engineering, materials science, transistor physics and semiconductor process knowledge.
• Experience with Semiconductor Device Physics, DRAM operations, wafer fabrication process flows, parametric/electrical test, and probe yield will be an added benefit to this position.
• Good data analysis, troubleshoot, problem solving, reporting and presentation skills.
• Good multi-tasking, verbal, and written communication skills.
• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.
• Good organizational capabilities and ability to work effectively with minimal supervision.
• Intermediate to advanced PC skills including Microsoft Office.
• Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities.
• Travel Required: Yes. Willing to travel as needed to support department goals
• Travel Frequency: 20-50%.

Education

• Bachelor’s degree and above in Electrical Engineering, Microelectronics, Physics, Chemistry, Materials Science or related field of study

Responsibilities :

• Establish Detection to have 100% Inline visibility and Inline control

• Improve Detection strategy, system, and methods to continuously strengthen detection performance.

• Enhance Detection capability and strategy to enable Yield improvement, improve Cycle of Learning and strengthen Defense Line.

• Establish and improve BKM (Best Known Method) related to RAM Detection performance, RAM detection cost and RAM supplier engagement

• Ensure BKM sharing spans across all sites regardless of technology and/or site mission differences.

• Set up process parameters for Inspection and Measurement equipment.

• Plan and Evaluate through supplier demo, tool evaluation or H2H (head to head) and Promote new equipment/ material through TOR (Tool of Record) process.

• Implement abnormal analysis and improvement.

• Facilitate and drive global peer groups (HVM and TD) to ensure alignment on strategy and roadmap to achieve area objectives

• Prioritize resources (internally across network and/or externally with Suppliers) to close any gaps.

• Lead Copy Smart Team (CST) and hold the teams accountable to deliver to timelines/commitments. Support cross sites alignment activities through CST and provide strategic direction for the team.

• Set Business Process to handle your area(s) of responsibility to meet the expectations of programs and business processes and adhere to the standards required by those programs and processes.

• Actively provide recommendations to improve and optimize programs and processes to the respective program and/or process owners.

• Be part of the team to handle global business for RAM area, including Tool of Records (TOR), Model of Records (MOR), Manufacturing Tool Evaluation Program (MTEP), DOC2, Executive Review Meeting (ERM), Supplier Change Notice (SCM) documentation etc.

• Keep Acceptance Documentation and Configuration Specs (ADCS) updated to current TOR configuration in your area(s) of responsibility.

• Handle projects with proper Project Management process with metric to track project success.

• Initiate, develop, drive and support strategies that not only benefit one site, but Micron network as a whole.

• Identify and share Best Known Method (BKM) across sites and track compliance to agreed upon alignment to BKMs.

• Track Fab performance metrics for benchmarking purposes. Identify gaps and area of improvements for Fabs.

• Partner with Technology Development and Global Procurement to drive suppliers' competitiveness in RDA and Metrology area to reduce CapEx and OpEx.

• Provide tactical support and coordination for the Fabs as required for issues of People, Safety, Time to Mature cummulative Yield, Quality, Cost, and Cycle Time.

• Engage and drive suppliers on Tool roadmap (MRM), Technology sharing, and other projects

Requirements :

• Masters/Bachelors in Engineering

• Relevant working experiences in RDA and/or Metrology

• Willing and capable of international travel, including Extended International Business Travel (EIBT) assignment to 6 months as needed, to accomplish the goals. Work with suppliers to address issues of spares delivery, quality, performance and change management.

• Good communication skill, maintain a strong and open relationship with peer group and appropriate team members in other functional areas such as Process Integration Engineering, Quality Systems, Production Operations Management, and Purchasing.

• Promote worldwide sharing and transfer of area-specific domain knowledge

Working Location : 1, North Coast Drive, Singapore 757432

Product Integration Engineering team strives to deliver pioneering process capability, best-in-class bits per wafer (Yield) with highest quality and fastest speed through innovation and collaboration with multi-functional team. With the diversity of technology in DRAM/NAND and geography (TD development sites – Boise/Japan, 5 manufacturing sites – US (F6), Taiwan (F11/F16), Japan (F15) and Singapore (F10)), Frontend Central PIE team will be responsible to identify best-known-method holistically, align best-known-method timely and implement improvement systematically across the network. As FE Central PIE Standardization & Metrics Senior Engineer you will be responsible to lead the the team on:

• Drive for alignment and standardization across various fabs on Best-Know-Methods (BKMs)
• Develop Metrics to measure the standardization, sustainability, scalability and synchronization of the BKMs.
• Identify gaps in current programs and use SMART metrics to drive effectiveness and efficiency on program deliverables.
• Transform yield SEAL and SWATs to achieve cPIE missions, improving network resource/talent leverage.
• Constantly drive productivity and eliminate inefficiency / ineffectiveness through metrics and reports automation, drive data to be accurate, accessible and comprehensive.
• Collaborate with various multi-functional teams on yield reports, develop business process to optimize current system with clear roles and responsibility.
• Promotes cPIE teams alignment and collaboration with crtical metrics /metrics definition.
• Collaborate with WFD to standardize network PIE training curriculum, connect with cPIE and network PIE to build training courses.
• Develop human resource strategies to attract, retain and reward talent and effectively deploy them to enhance every individual’s potential
• Engage team members and drive accountability, performance driven culture through clear communication, formal and informal feedback, goals and critical metric
• Drive diversity, equality, and inclusive working environment and foster teamwork and trust in the organization
• Effectively manage team’s internal and worldwide meeting structure. Ensure meetings are efficient, effective and targeted to achieve required outcomes.
• Maintain knowledge of equipment and materials safety concerns. Take a proactive approach to safety, and apply corporate and site safety resources for partner concern issues as appropriate.
• Maintain a strong and open relationship with peer group and managers in other functional areas within CPIE and outside organizations such as Fab, FE PMO/SIC/OCT and Global Quality.
• Travel to Micron sites as necessary for face to face collaboration.

Requirements:

• Bachelor’s Degree in Engineering and related field of study
• 2 years experience in engineering field
• Applicants must have a proven ability to collaborate globally and influence by indirect leadership to drive resourcing to critical projects across Micron
• Applicants must have a proven capability in dealing with complexity and an ability to use resources effectively to bring clarity to required actions
• Applicants must hold a record of performance excellence for current area of responsibility; and are recognized as having demonstrated successful leadership characteristics both in present and past jobs
• Applicants must have demonstrated the ability to solve problems across multi-functional groups, both within and outside their department/Site

As Satellite Planning Engineer, you are responsible to simplify and eliminate manual error through task automation. You will be developing automation for scenario modeling and capital dashboard reporting to provide overview for upper management and give insight for decision making.

This role requires strong programming skill for task automation and scenario analysis with at least 2 years experiences in coding/programming languages or have done automation project related to scenario modeling, data analysis and reporting. Candidates should be flexible, able to maintain global relationships, and possess good communication and presentation skills. Additionally, they need to provide clear data analysis for decision-making and have a detailed understanding of capacity planning, business processes, and scenario optimization opportunities.

Job Description

As Satellite Planning Engineer, you are responsible to simplify and eliminate manual error through task automation. You will be developing automation for scenario modeling and capital dashboard reporting to provide overview for upper management and give insight for decision making.

This role requires strong programming skill for task automation and scenario analysis with at least 2 years experiences in coding/programming languages or have done automation project related to scenario modeling, data analysis and reporting. Candidates should be flexible, able to maintain global relationships, and possess good communication and presentation skills. Additionally, they need to provide clear data analysis for decision-making and have a detailed understanding of capacity planning, business processes, and scenario optimization opportunities.

Responsibilities and Tasks:

[Scenario & Capital Automation Project]

· Develop capital related dashboards to achieve automated data visualization and assist in a more in-depth analysis of site capital expenditure details

· Strive to streamline business efficiency and eliminate manual errors through task automation and simplification.

· Build and automate scenario modeling to support scenario analysis with improved efficiency and accuracy

· Manage databases, scenario ownership and change control

· Analyze data to support financial decisions

· Create, Maintain and update Satellite Sharepoint as golden source of historically approved loading scenarios together with its key metric impact such as capital add/reduction, bit, market share, wafer cost etc.

[Scenario]

· Apply optimization concept and technique to ensure optimal loading volume across horizon able to meet target bit (GB) and market share while considering new technode qual achievement and ramp planning.

· Apply industrial engineering concepts to model the capacity thresholds to support existing and future technology

· Ensure all the required scenario options are well analyzed. Call out opportunity and propose options for better return scenario

· Collaborate with Central teams to plan capacity requirements of future products and to quantify the impact on existing and future capital spend

· Using qualitative and quantitative analysis to explain scenario cause – effect relationship for tooling purchase and capital impact differences

· Provide yellow field Cost of Transition (CoT) for each technode and understand the correlation between theoretical CoT vs actual CoT

· Defining new technode CoT and understand the gap between budget vs actual technode capex

· Adhere to calendar requirements and agreements with respect to Business Planning Process

· Flexible and agile to changes in Business Planning

· Coordinate with all relevant partners to ensure all the parameters updates are in-place so that can be applied correctly for quarterly business plan study

[Capital]

· Perform baseline capital spend analysis to ensure overall cashflow across Fiscal Year is kept neutral (unless driven by loading change)

· Improve capital spend forecast accuracy with site Planning/Procurement/Facilities

· Monitor actual spend performance vs projection for current and upcoming quarter with target variance of < +- 5%

· Monitor and understand with site partners on the reasons for unexpected capital spend changes across fiscal year

· Work with site partners to ensure accurate planning and supplier delivery date data inside Capital Asset Lifecycle Management (CALM)

· Highlight any potential cashflow reduction or savings opportunities

· Keep track of the technode CAPEX

· Work with site partners to ensure actual Scenario Study bottoms up and eventual itemization is as per approved executive review targets

· Coordinate the CALM simulations with site partners and ensure the simulations are able achieve net neutral and completed within committed timeline

Requirements:

· Master/Bachelor's Degree in Industrial Engineering, Manufacturing engineering, Mechanical engineering, Chemical engineering, Computer Science

· Min 2 years experiences/project hands-on in developing automation using programming language such as Python, Java or C+

· Proficiency in developing dashboard and reports using Tableau and Power BI

· Skillful in Microsoft Office particularly Excel as well as Sharepoint management.

· Strong ability to perform data analysis and problem solving

· Strong data validation skills and reporting skills

· Ability to map relevant conclusions to support decisions making

· Ability to work closely and effectively with others in a team environment

· Strong verbal communication and presentation skills

Working location:

· 1, North Coast Drive, Singapore 757432

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities

• Leading the design, development and characterization of new tools and identifying and closing any hardware and procedural gaps.
• Innovate solutions that enable best in class performance
• Oversee installation and upgrades of tools ensuring quality of work, cost control and alignment to project schedule.
• Engage equipment vendors to improve current products and implement roadmap needs.
• Work with Process Engineers, Manufacturing, Procurement, and Vendor partners to develop a comprehensive package capable for our volume manufacturing sites.
• Generating and maintaining documents that outline equipment performance, operating procedures, maintenance specifications, and cost metrics.
• Support Internal And External Audits

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above

Location: Fab10N

Closing Date: Until filled

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• Process module ownership involving regE process characterizations and advanced process developments for 3D NAND and beyond.
• Work with process development engineers in Singapore and Boise, US TD site and vendors to develop regE processes that meet integration requirements for next-generation 3-D NAND nodes.
• Transfer regE processes to high volume manufacturing (Fab10), and work on continuous improvements to manufacturability.
• Address specific wafer edge issues (such as bevel defects, uniformity issues), working with Fab10N team and with key business partners on tool choices for manufacturing, evaluations etc., as applicable.
• Focus on understanding and improving regE process margins required for meeting the mature yield goal for 3D NAND parts.
• Initiate and manage experiments to widen regE process margins as well as to test out manufacturability of next node solutions
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Serve as a technical expert within Micron contributing to technical projects for improvements to processes, procedures and equipment.
• Define and leads complex, multi-functional projects of critical importance to Micron, helps to define strategic direction.
• Lead team or sites or suppliers on complex, multi-disciplinary projects in quality focused meetings, process and yield improvement meetings, cost and productivity improvement meetings
• Provide advice and counsel to management on significant technical issues. Leads and initiate innovation projects through patents/technical papers.
• This position requires communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Be part of the continuous worldwide TD engagement with suppliers pushing for breakthrough solutions.

Requirements

• Bachelors’ degree or higher in Materials Science, Chemical Engineering or Physics with minimum 2 years hands-on experiences in relevant regE process developments.
• Familiarity with regE process developments and yield improvements.
• Understanding of various integration and structural impacts and constraints related to wafer edge.
• An understanding of the general process steps and process flow for memory processing, planar and vertical NAND memory in particular.
• Working knowledge of data analysis systems e.g.: Y3 to facilitate analysis of experimental data
• Working knowledge of Design of Experiments (DoE)
• Proven ability to collaborate with local and overseas teams on projects
• Excellent oral and written communication skills with ability to convey the message in concise and effective manner both in local as well as remote communications.
• Ability to be a self-motivated individual and be adaptable to Micron’s changing needs in terms of working extended hours, if required
• Proven ability to work in a demanding & dynamic environment and able to prioritize and manage multiple projects simultaneously
• Ability to travel for extended periods of time and stay at Boise TD for 4-6 months at a stretch to work on technology development.

As a Senior NAND Cell Device Engineer, in the Singapore Device Technology Development group of Micron Technology Inc., you will be responsible for electrical characterization of the NAND memory cell and develop novel device solutions for cutting-edge 3D-NAND flash technologies. You will have an exciting opportunity to develop best-in class non-volatile memories and products in the world!

Job responsibilities:

• Develop an understanding of performance & reliability requirements for new NAND cells and help refine requirements, as necessary.
• Characterize NAND Memory cell and array properties to identify device improvement directions.
• Analyse automated tester data to establish product qualification gaps, identify new device corners and improve detection capabilities.
• Contribute to the architecture and process definition for state-of-the-art NAND cell, by providing expertise in NAND device physics and array operation.
• Collaborate effectively with process, integration, product, and design engineers, to address NAND memory cell deficits and deliver improvement roadmaps.

Requirements:

• M.S or Ph.D. in Electrical or Electronics Engineering, Physics or Materials Science Engineering or similar.
• 3+ years of work experience in CMOS or non-volatile memory is preferred.
• Deep understanding of semiconductor device physics and processes.
• Knowledge of statistical methods for experiment design and data analysis.
• Solid communication and reporting abilities.
• The ability to be highly skilled at driving for results.

As a Process Engineer you will be primarily responsible for starting up, developing and optimizing processes to improve product quality and reliability, working on process yield improvement, cost reduction, productivity improvement and risk management as well as resolving manufacturing line problems. You will also be required to identify, diagnose and resolve assembly process related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology. Additional responsibilities include coordinating and carrying out process, equipment and material evaluation/optimization/development to implement changes at process step, leading and participating in yield improvement and cost reduction activities, handling new process baseline qualifications and managing, auditing and liaising with equipment/material suppliers to achieve yield, quality, cost and risk management objectives.

Micron’s NAND Technology Integration (NTI) Singapore R&D group is looking for process development engineer to support R&D activities associated with rapid deployment of technology nodes, the process margin improvement work necessitated thereof as well as to ensure extended engagement with manufacturing on the upcoming technology nodes.

Responsibilities

• Develop and optimize unit processes to meet the yield and quality requirements of advanced NAND products.
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement
• Prioritize within Singapore based manufacturing CVD/PVD teams on the key technology issues that need R&D breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement
• Participate with Boise R&D Films peers on technology choices for the upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work with manufacturing and Boise R&D to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Initiate and manage experiments to widen process margins as well as to test out manufacturability of next node solutions
• Identify process simplification opportunities and drive cross functional teams in implementation
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Serve as a technical expert within Micron contributing to technical projects for improvements to processes, procedures and equipment.
• Lead team or sites or suppliers on complex, multi-disciplinary projects in quality focused meetings, process and yield improvement meetings, cost and productivity improvement meetings
• Provide advice and counsel to management on significant technical issues. Leads and initiate innovation projects through patents/technical papers.
• This position requires communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Be part of the continuous worldwide R&D engagement with suppliers pushing for breakthrough solutions.

Requirements

• Master degree or higher in Materials Science, Chemical/Microelectronic Engineering, or Physics with minimum 3 years hands-on experience in leading edge film deposition/implant technology work. Fresh PhD/Masters graduates in Materials Science, Chemical/Microelectronic Engineering or Physics are also welcome to apply.
• A deep understanding of chemical kinetics, thermodynamics, physical phenomena and their direct application to CVD/PVD deposition in various deposition methods.
• An ability to understand and troubleshoot precursor depletion effects within three dimensional structures and come up with innovative ideas to mitigate the effects.
• Basic understanding of films and interface engineering and analysis techniques thereof – SIMS, XPS, EDX, SEM/TEM.
• Understanding of various integration and structural impacts and constraints related to film deposition processes.
• An understanding of the general process steps and process flow for memory processing, planar and vertical NAND memory in particular.
• Working knowledge of data analysis systems e.g.: Y3 to facilitate analysis of experimental data
• Working knowledge of Design of Experiments (DoE)
• Proven ability to collaborate with local and overseas teams on projects
• Excellent oral and written communication skills with ability to convey the message in concise and effective manner both in local as well as remote communications.
• Ability to be a self-motivated individual and be adaptable to Micron’s changing needs in terms of working extended hours, if required
• Proven ability to work in a demanding & dynamic environment and able to prioritize and manage multiple projects simultaneously
• Ability to travel for extended periods of time and stay at Boise R&D for 4-6 months at a stretch to work on technology development.

As a NAND CMOS Device Engineer, you will help set the direction for current and future CMOS technology for Micron’s NAND Memory Technology Roadmap!

You will work with the Design Team to set electrical targets and define transistor structures to meet these targets. You will guide the device technology development and be in close relation with Process Integration, Design Engineering, Design, Design Rules, Reliability, Transistor Modeling, TCAD (Technology Computer-Aided Design), and Parametric Test, to name a few! In addition, you will ensure that the developed technology is manufacturable and highly yielding and that these considerations are designed into the technology from the start.

Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps

• You give directions on how to improve our device portfolio, both in performance and cost effectiveness
• You define, execute, and analyze silicon experiments for future device generations
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules
• Work with TCAD simulation group to develop strategies for transistor structures to meet targets
• You strive to ensure that transistor models are correctly targeted to anticipate final silicon
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring
• Highly motivated to ensure transistors are developed meeting the required reliability standards
• You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues
• You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues

Minimum Qualifications:

• MS/PhD in Electrical Engineering or related field, PhD in Semiconductor Device Technology preferred
• 5 plus years industry experience in the field of CMOS device design, simulation, characterization
• Experience in developing advanced logic transistor technologies
• Experience in developing Analog FETs operating at higher Voltages
• Preferred: Experience in the field of High Voltage applications, reliability, characterization, device development
• Understanding of analog design concepts
• Good presentation skills
• Excellent team and mentoring skills

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

Description

As a NAND CMOS Process Integration Engineer in the Singapore Technology Development department at Micron Technology Inc., you will be responsible for developing 3D NAND CMOS devices scaling and enhancing their performance, reliability and manufacturability.

Responsibilities:

• Develop and innovate critical CMOS modules. Drive multi-functional teams to optimize existing process flows and develop new innovative solutions to meet product requirements and manufacturability.
• Develop/re-define critical specifications criteria for optimum product performance and drive activities to get them to manufacturing process capability.
• Extract and analyze inline, probe, parametric, reliability, and other critical metrics and predict future behavior of the CMOS device performance of the product to enable early innovative solutions to meet product and device specifications.
• Early introduction, characterization and validation of new CMOS device models and test structures for developing future NAND products.
• 3 dimensions analysis with the use of K2 view to extract layout information and combine with the doping profiles of each implant step for product development and integration solutions.
• Interact and collaborate with TCAD, modeling, and layout teams to drive clearer definition of CMOS device and reliability improvements across multiple tech-nodes and designs.
• Coordinate activities at manufacturing site towards gating experiment funding, conversions, and effectively communicate decisions made to all R&D, manufacturing, and relevant partners.
• Take on leadership role at quarterly yield summits and monthly program reviews in summarizing complex problems, deriving and explaining actions taken to address them and getting R&D, manufacturing, and senior management teams on the same page.
• Assist in the transfer of a new technology from R&D to manufacturing and contribute towards ensuring successful ramp and qualification. Supporting the transfer, documentation and training of module fundamentals into manufacturing.

Requirements:

• MS or PhD in Electrical Engineering preferably specialized in Microelectronics and Semiconductor Device Physics. Prior technology development and tech transfer/manufacturing experiences are preferred.
• Fresh MS/PhD candidates with knowledge of semiconductor process Integration, device physics and CMOS engineering.
• Direct fab experience with nonvolatile memories manufacturing, knowledge of TCAD, K2 view layout, and NAND product are highly desirable.
• Ability to develop a strong, holistic, end-to-end understanding of CMOS device and its related module on NAND technologies, related structural and electrical fail mechanisms.
• Deep understanding of probe failure mechanism, ability to do electrical bench data collection.
• Self-motivated, self-governing with proven ability to work in a demanding and dynamic environment.
• Experienced in coordinating cross-functional teams to achieve a goal.
• Solid data analysis, communication and reporting abilities with demonstrated presentation abilities.
• Curiosity and natural tendency of learning new things independently.
• Ability to travel for extended periods of time to the US for collaborative R&D work.

Working Location: Fab10, 1 North Coast Drive, Singapore 757432