Total 300 quality control engineer job vacancies in Singapore

Responsibilities :

Equipment Performance

• Come up with methodologies to improve %UD/SD performance globally.
• Design Tier 2/3 matrices to improve %UD/SD.
• Develop suitable global reports for sites to benchmark against each other on %UD/SD
• Design and implement a process to improve workstations MOR %UTIL through %MA & Lost time improvement.
• Study the wafer path taken in critical workstations.
• Identify key data that needs to be extracted from the tool EDA system to map the time taken to complete wafer processing.
• Collaborate with SMAI to build a system to compare the wafer processing time between tools within a workstation.
• Quantify capex avoidance/savings that arise from improving Equipment Performance.

Address Tool to Tool mismatches in Process Areas

• Build a database of inputs for all process areas to address tool to tool mismatch proactively.
• Database of inputs should cover the cross matching of software, hardware & process related inputs.
• Collaborate with SMAI to build a system using these inputs to identify & fix tool to tool mismatches in a workstation.
• Appropriate measures, processes, and metrics should be devised to handle and maintain tool to tool mismatches effectively.

Standardization of practices & BKMs in Process Areas

• Setup global area alignment teams to address chronic issues, drive improvements & eliminate wastes.
• Channel improvements and lessons learnt established from various forums, eg. TPM Forum, Excursion Review, etc.  into global area forums to decide on the standards for deployment, implementation and audit.
• Design suitable matrices for each process area so that improvements impact the 4 pillars.
• Create a library of area level BKMs for Equipment & Process Engineers to search for standards involving the setup of Equipment & associated processes.
• This library must also serve the purpose to feed-forward area level BKMs to TD for process development & HVM for improvement work that will impact the 4 pillars.
• Sit in transfer reviews to ensure N-1 standards are fed-forward to N technode for sustenance

Demonstrate Leadership

• Adopt benchmarking and deliver strategies to close the gaps.
• Challenge complacency and do not let strong market conditions give a false sense of reality.
• Gain insights into the competitor's culture, approach, and capabilities.
• Understand that the only way to guarantee our future is to be the best.
• Understand the challenges your team faces.
• Don’t underestimate the effort it takes to be number one.
• Ignite the passion in people to achieve the impossible.
• Dare to set high targets, expect innovation and breakthroughs.
• Give honest, tough, but productive feedback to the team, and be willing to receive it yourself.
• Challenge others and be willing to stand for something.
• Have the courage to turn a crisis into an opportunity.
• Lead from the front and lead by example.
• Become the team that will out-innovate and out-execute the competition. Don’t accept anything less.
• Be unrelenting and “unreasonable”.
• Cultivate a habit of winning. Winning breed’s confidence.
• Find top talent willing to take risk and support them in doing the exceptional.
• Face unsolvable problems head-on and turn them into opportunities.
• Develop teams and team members to enable them to reach their full potential and reward them accordingly.
• Support team members with coaches and mentors who push TM outside their comfort zone.
• Lead the team to success.
• Leave a legacy behind that we are proud of.
• Believe in your team.

Requirements :

• Bachelors Degree in Electrical / Electronics / Semiconductor Engineering
• 10 years of experience and/or demonstrated ability in any of the following Field (Equipment or/& Process)
• Preferably experienced in Photo & PCVD area.
• Applicants must have a consistent record to collaborate globally and influence by indirect leadership in order to drive resourcing to critical projects across Micron.
• Applicants must have a shown capability in dealing with complexity and an ability to apply resources effectively to bring clarity to required actions.
• Applicants must hold a record of performance excellence for current area of responsibility; and are recognized as having demonstrated successful leadership characteristics both in present and past jobs.
• Applicants are viewed by current reports as an excellent mentor, team builder and motivator.
• Applicants must have demonstrated the ability to solve problems across multi-functional groups, both within and outside their department/Site.
• Applicants must have experience handling large, multi-layer groups that encompass a variety of fields.
• Applicants must have proficiency in handling through systems, informing, organizational agility, dealing with ambiguity, and listening. They must demonstrate a strong alignment with Micron Behaviors and the skills they'll use every day.

Responsibilities :

• Establish Detection to have 100% Inline visibility and Inline control

• Improve Detection strategy, system, and methods to continuously strengthen detection performance.

• Enhance Detection capability and strategy to enable Yield improvement, improve Cycle of Learning and strengthen Defense Line.

• Establish and improve BKM (Best Known Method) related to RAM Detection performance, RAM detection cost and RAM supplier engagement

• Ensure BKM sharing spans across all sites regardless of technology and/or site mission differences.

• Set up process parameters for Inspection and Measurement equipment.

• Plan and Evaluate through supplier demo, tool evaluation or H2H (head to head) and Promote new equipment/ material through TOR (Tool of Record) process.

• Implement abnormal analysis and improvement.

• Facilitate and drive global peer groups (HVM and TD) to ensure alignment on strategy and roadmap to achieve area objectives

• Prioritize resources (internally across network and/or externally with Suppliers) to close any gaps.

• Lead Copy Smart Team (CST) and hold the teams accountable to deliver to timelines/commitments. Support cross sites alignment activities through CST and provide strategic direction for the team.

• Set Business Process to handle your area(s) of responsibility to meet the expectations of programs and business processes and adhere to the standards required by those programs and processes.

• Actively provide recommendations to improve and optimize programs and processes to the respective program and/or process owners.

• Be part of the team to handle global business for RAM area, including Tool of Records (TOR), Model of Records (MOR), Manufacturing Tool Evaluation Program (MTEP), DOC2, Executive Review Meeting (ERM), Supplier Change Notice (SCM) documentation etc.

• Keep Acceptance Documentation and Configuration Specs (ADCS) updated to current TOR configuration in your area(s) of responsibility.

• Handle projects with proper Project Management process with metric to track project success.

• Initiate, develop, drive and support strategies that not only benefit one site, but Micron network as a whole.

• Identify and share Best Known Method (BKM) across sites and track compliance to agreed upon alignment to BKMs.

• Track Fab performance metrics for benchmarking purposes. Identify gaps and area of improvements for Fabs.

• Partner with Technology Development and Global Procurement to drive suppliers' competitiveness in RDA and Metrology area to reduce CapEx and OpEx.

• Provide tactical support and coordination for the Fabs as required for issues of People, Safety, Time to Mature cummulative Yield, Quality, Cost, and Cycle Time.

• Engage and drive suppliers on Tool roadmap (MRM), Technology sharing, and other projects

Requirements :

• Masters/Bachelors in Engineering

• Relevant working experiences in RDA and/or Metrology

• Willing and capable of international travel, including Extended International Business Travel (EIBT) assignment to 6 months as needed, to accomplish the goals. Work with suppliers to address issues of spares delivery, quality, performance and change management.

• Good communication skill, maintain a strong and open relationship with peer group and appropriate team members in other functional areas such as Process Integration Engineering, Quality Systems, Production Operations Management, and Purchasing.

• Promote worldwide sharing and transfer of area-specific domain knowledge

Working Location : 1, North Coast Drive, Singapore 757432

Product Integration Engineering team strives to deliver pioneering process capability, best-in-class bits per wafer (Yield) with highest quality and fastest speed through innovation and collaboration with multi-functional team. With the diversity of technology in DRAM/NAND and geography (TD development sites – Boise/Japan, 5 manufacturing sites – US (F6), Taiwan (F11/F16), Japan (F15) and Singapore (F10)), Frontend Central PIE team will be responsible to identify best-known-method holistically, align best-known-method timely and implement improvement systematically across the network. As FE Central PIE Standardization & Metrics Senior Engineer you will be responsible to lead the the team on:

• Drive for alignment and standardization across various fabs on Best-Know-Methods (BKMs)
• Develop Metrics to measure the standardization, sustainability, scalability and synchronization of the BKMs.
• Identify gaps in current programs and use SMART metrics to drive effectiveness and efficiency on program deliverables.
• Transform yield SEAL and SWATs to achieve cPIE missions, improving network resource/talent leverage.
• Constantly drive productivity and eliminate inefficiency / ineffectiveness through metrics and reports automation, drive data to be accurate, accessible and comprehensive.
• Collaborate with various multi-functional teams on yield reports, develop business process to optimize current system with clear roles and responsibility.
• Promotes cPIE teams alignment and collaboration with crtical metrics /metrics definition.
• Collaborate with WFD to standardize network PIE training curriculum, connect with cPIE and network PIE to build training courses.
• Develop human resource strategies to attract, retain and reward talent and effectively deploy them to enhance every individual’s potential
• Engage team members and drive accountability, performance driven culture through clear communication, formal and informal feedback, goals and critical metric
• Drive diversity, equality, and inclusive working environment and foster teamwork and trust in the organization
• Effectively manage team’s internal and worldwide meeting structure. Ensure meetings are efficient, effective and targeted to achieve required outcomes.
• Maintain knowledge of equipment and materials safety concerns. Take a proactive approach to safety, and apply corporate and site safety resources for partner concern issues as appropriate.
• Maintain a strong and open relationship with peer group and managers in other functional areas within CPIE and outside organizations such as Fab, FE PMO/SIC/OCT and Global Quality.
• Travel to Micron sites as necessary for face to face collaboration.

Requirements:

• Bachelor’s Degree in Engineering and related field of study
• 2 years experience in engineering field
• Applicants must have a proven ability to collaborate globally and influence by indirect leadership to drive resourcing to critical projects across Micron
• Applicants must have a proven capability in dealing with complexity and an ability to use resources effectively to bring clarity to required actions
• Applicants must hold a record of performance excellence for current area of responsibility; and are recognized as having demonstrated successful leadership characteristics both in present and past jobs
• Applicants must have demonstrated the ability to solve problems across multi-functional groups, both within and outside their department/Site

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• Process module ownership involving regE process characterizations and advanced process developments for 3D NAND and beyond.
• Work with process development engineers in Singapore and Boise, US TD site and vendors to develop regE processes that meet integration requirements for next-generation 3-D NAND nodes.
• Transfer regE processes to high volume manufacturing (Fab10), and work on continuous improvements to manufacturability.
• Address specific wafer edge issues (such as bevel defects, uniformity issues), working with Fab10N team and with key business partners on tool choices for manufacturing, evaluations etc., as applicable.
• Focus on understanding and improving regE process margins required for meeting the mature yield goal for 3D NAND parts.
• Initiate and manage experiments to widen regE process margins as well as to test out manufacturability of next node solutions
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Serve as a technical expert within Micron contributing to technical projects for improvements to processes, procedures and equipment.
• Define and leads complex, multi-functional projects of critical importance to Micron, helps to define strategic direction.
• Lead team or sites or suppliers on complex, multi-disciplinary projects in quality focused meetings, process and yield improvement meetings, cost and productivity improvement meetings
• Provide advice and counsel to management on significant technical issues. Leads and initiate innovation projects through patents/technical papers.
• This position requires communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Be part of the continuous worldwide TD engagement with suppliers pushing for breakthrough solutions.

Requirements

• Bachelors’ degree or higher in Materials Science, Chemical Engineering or Physics with minimum 2 years hands-on experiences in relevant regE process developments.
• Familiarity with regE process developments and yield improvements.
• Understanding of various integration and structural impacts and constraints related to wafer edge.
• An understanding of the general process steps and process flow for memory processing, planar and vertical NAND memory in particular.
• Working knowledge of data analysis systems e.g.: Y3 to facilitate analysis of experimental data
• Working knowledge of Design of Experiments (DoE)
• Proven ability to collaborate with local and overseas teams on projects
• Excellent oral and written communication skills with ability to convey the message in concise and effective manner both in local as well as remote communications.
• Ability to be a self-motivated individual and be adaptable to Micron’s changing needs in terms of working extended hours, if required
• Proven ability to work in a demanding & dynamic environment and able to prioritize and manage multiple projects simultaneously
• Ability to travel for extended periods of time and stay at Boise TD for 4-6 months at a stretch to work on technology development.

As a Senior NAND Cell Device Engineer, in the Singapore Device Technology Development group of Micron Technology Inc., you will be responsible for electrical characterization of the NAND memory cell and develop novel device solutions for cutting-edge 3D-NAND flash technologies. You will have an exciting opportunity to develop best-in class non-volatile memories and products in the world!

Job responsibilities:

• Develop an understanding of performance & reliability requirements for new NAND cells and help refine requirements, as necessary.
• Characterize NAND Memory cell and array properties to identify device improvement directions.
• Analyse automated tester data to establish product qualification gaps, identify new device corners and improve detection capabilities.
• Contribute to the architecture and process definition for state-of-the-art NAND cell, by providing expertise in NAND device physics and array operation.
• Collaborate effectively with process, integration, product, and design engineers, to address NAND memory cell deficits and deliver improvement roadmaps.

Requirements:

• M.S or Ph.D. in Electrical or Electronics Engineering, Physics or Materials Science Engineering or similar.
• 3+ years of work experience in CMOS or non-volatile memory is preferred.
• Deep understanding of semiconductor device physics and processes.
• Knowledge of statistical methods for experiment design and data analysis.
• Solid communication and reporting abilities.
• The ability to be highly skilled at driving for results.

As a Process Engineer you will be primarily responsible for starting up, developing and optimizing processes to improve product quality and reliability, working on process yield improvement, cost reduction, productivity improvement and risk management as well as resolving manufacturing line problems. You will also be required to identify, diagnose and resolve assembly process related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology. Additional responsibilities include coordinating and carrying out process, equipment and material evaluation/optimization/development to implement changes at process step, leading and participating in yield improvement and cost reduction activities, handling new process baseline qualifications and managing, auditing and liaising with equipment/material suppliers to achieve yield, quality, cost and risk management objectives.

Micron’s NAND Technology Integration (NTI) Singapore R&D group is looking for process development engineer to support R&D activities associated with rapid deployment of technology nodes, the process margin improvement work necessitated thereof as well as to ensure extended engagement with manufacturing on the upcoming technology nodes.

Responsibilities

• Develop and optimize unit processes to meet the yield and quality requirements of advanced NAND products.
• Quantify benefits of innovative process and/or equipment solutions to enable early experimentation and adoption for process margin improvement
• Prioritize within Singapore based manufacturing CVD/PVD teams on the key technology issues that need R&D breakthroughs.
• Integrate and troubleshoot processes as part of cross-functional teams driving yield and quality improvement
• Participate with Boise R&D Films peers on technology choices for the upcoming nodes and able to translate future technology device needs into clear process requirements
• Identify disruptive processes early on and work with manufacturing and Boise R&D to identify viable path forward
• Process development will include performing fundamental research, hardware evaluations, as well as testing processes for novel applications and generating intellectual property relevant to Micron.
• Initiate and manage experiments to widen process margins as well as to test out manufacturability of next node solutions
• Identify process simplification opportunities and drive cross functional teams in implementation
• Incorporate best known manufacturing methods into early development phase of upcoming nodes.
• Design and implement advanced process monitoring and control methodologies.
• Serve as a technical expert within Micron contributing to technical projects for improvements to processes, procedures and equipment.
• Lead team or sites or suppliers on complex, multi-disciplinary projects in quality focused meetings, process and yield improvement meetings, cost and productivity improvement meetings
• Provide advice and counsel to management on significant technical issues. Leads and initiate innovation projects through patents/technical papers.
• This position requires communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Be part of the continuous worldwide R&D engagement with suppliers pushing for breakthrough solutions.

Requirements

• Master degree or higher in Materials Science, Chemical/Microelectronic Engineering, or Physics with minimum 3 years hands-on experience in leading edge film deposition/implant technology work. Fresh PhD/Masters graduates in Materials Science, Chemical/Microelectronic Engineering or Physics are also welcome to apply.
• A deep understanding of chemical kinetics, thermodynamics, physical phenomena and their direct application to CVD/PVD deposition in various deposition methods.
• An ability to understand and troubleshoot precursor depletion effects within three dimensional structures and come up with innovative ideas to mitigate the effects.
• Basic understanding of films and interface engineering and analysis techniques thereof – SIMS, XPS, EDX, SEM/TEM.
• Understanding of various integration and structural impacts and constraints related to film deposition processes.
• An understanding of the general process steps and process flow for memory processing, planar and vertical NAND memory in particular.
• Working knowledge of data analysis systems e.g.: Y3 to facilitate analysis of experimental data
• Working knowledge of Design of Experiments (DoE)
• Proven ability to collaborate with local and overseas teams on projects
• Excellent oral and written communication skills with ability to convey the message in concise and effective manner both in local as well as remote communications.
• Ability to be a self-motivated individual and be adaptable to Micron’s changing needs in terms of working extended hours, if required
• Proven ability to work in a demanding & dynamic environment and able to prioritize and manage multiple projects simultaneously
• Ability to travel for extended periods of time and stay at Boise R&D for 4-6 months at a stretch to work on technology development.

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities

• Leading the design, development and characterization of new tools and identifying and closing any hardware and procedural gaps.
• Innovate solutions that enable best in class performance
• Oversee installation and upgrades of tools ensuring quality of work, cost control and alignment to project schedule.
• Engage equipment vendors to improve current products and implement roadmap needs.
• Work with Process Engineers, Manufacturing, Procurement, and Vendor partners to develop a comprehensive package capable for our volume manufacturing sites.
• Generating and maintaining documents that outline equipment performance, operating procedures, maintenance specifications, and cost metrics.
• Support Internal And External Audits

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above

Location: Fab10N

Closing Date: Until filled

As Satellite Planning Engineer, you are responsible to simplify and eliminate manual error through task automation. You will be developing automation for scenario modeling and capital dashboard reporting to provide overview for upper management and give insight for decision making.

This role requires strong programming skill for task automation and scenario analysis with at least 2 years experiences in coding/programming languages or have done automation project related to scenario modeling, data analysis and reporting. Candidates should be flexible, able to maintain global relationships, and possess good communication and presentation skills. Additionally, they need to provide clear data analysis for decision-making and have a detailed understanding of capacity planning, business processes, and scenario optimization opportunities.

Job Description

As Satellite Planning Engineer, you are responsible to simplify and eliminate manual error through task automation. You will be developing automation for scenario modeling and capital dashboard reporting to provide overview for upper management and give insight for decision making.

This role requires strong programming skill for task automation and scenario analysis with at least 2 years experiences in coding/programming languages or have done automation project related to scenario modeling, data analysis and reporting. Candidates should be flexible, able to maintain global relationships, and possess good communication and presentation skills. Additionally, they need to provide clear data analysis for decision-making and have a detailed understanding of capacity planning, business processes, and scenario optimization opportunities.

Responsibilities and Tasks:

[Scenario & Capital Automation Project]

· Develop capital related dashboards to achieve automated data visualization and assist in a more in-depth analysis of site capital expenditure details

· Strive to streamline business efficiency and eliminate manual errors through task automation and simplification.

· Build and automate scenario modeling to support scenario analysis with improved efficiency and accuracy

· Manage databases, scenario ownership and change control

· Analyze data to support financial decisions

· Create, Maintain and update Satellite Sharepoint as golden source of historically approved loading scenarios together with its key metric impact such as capital add/reduction, bit, market share, wafer cost etc.

[Scenario]

· Apply optimization concept and technique to ensure optimal loading volume across horizon able to meet target bit (GB) and market share while considering new technode qual achievement and ramp planning.

· Apply industrial engineering concepts to model the capacity thresholds to support existing and future technology

· Ensure all the required scenario options are well analyzed. Call out opportunity and propose options for better return scenario

· Collaborate with Central teams to plan capacity requirements of future products and to quantify the impact on existing and future capital spend

· Using qualitative and quantitative analysis to explain scenario cause – effect relationship for tooling purchase and capital impact differences

· Provide yellow field Cost of Transition (CoT) for each technode and understand the correlation between theoretical CoT vs actual CoT

· Defining new technode CoT and understand the gap between budget vs actual technode capex

· Adhere to calendar requirements and agreements with respect to Business Planning Process

· Flexible and agile to changes in Business Planning

· Coordinate with all relevant partners to ensure all the parameters updates are in-place so that can be applied correctly for quarterly business plan study

[Capital]

· Perform baseline capital spend analysis to ensure overall cashflow across Fiscal Year is kept neutral (unless driven by loading change)

· Improve capital spend forecast accuracy with site Planning/Procurement/Facilities

· Monitor actual spend performance vs projection for current and upcoming quarter with target variance of < +- 5%

· Monitor and understand with site partners on the reasons for unexpected capital spend changes across fiscal year

· Work with site partners to ensure accurate planning and supplier delivery date data inside Capital Asset Lifecycle Management (CALM)

· Highlight any potential cashflow reduction or savings opportunities

· Keep track of the technode CAPEX

· Work with site partners to ensure actual Scenario Study bottoms up and eventual itemization is as per approved executive review targets

· Coordinate the CALM simulations with site partners and ensure the simulations are able achieve net neutral and completed within committed timeline

Requirements:

· Master/Bachelor's Degree in Industrial Engineering, Manufacturing engineering, Mechanical engineering, Chemical engineering, Computer Science

· Min 2 years experiences/project hands-on in developing automation using programming language such as Python, Java or C+

· Proficiency in developing dashboard and reports using Tableau and Power BI

· Skillful in Microsoft Office particularly Excel as well as Sharepoint management.

· Strong ability to perform data analysis and problem solving

· Strong data validation skills and reporting skills

· Ability to map relevant conclusions to support decisions making

· Ability to work closely and effectively with others in a team environment

· Strong verbal communication and presentation skills

Working location:

· 1, North Coast Drive, Singapore 757432

As a NAND CMOS Device Engineer, you will help set the direction for current and future CMOS technology for Micron’s NAND Memory Technology Roadmap!

You will work with the Design Team to set electrical targets and define transistor structures to meet these targets. You will guide the device technology development and be in close relation with Process Integration, Design Engineering, Design, Design Rules, Reliability, Transistor Modeling, TCAD (Technology Computer-Aided Design), and Parametric Test, to name a few! In addition, you will ensure that the developed technology is manufacturable and highly yielding and that these considerations are designed into the technology from the start.

Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps

• You give directions on how to improve our device portfolio, both in performance and cost effectiveness
• You define, execute, and analyze silicon experiments for future device generations
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules
• Work with TCAD simulation group to develop strategies for transistor structures to meet targets
• You strive to ensure that transistor models are correctly targeted to anticipate final silicon
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring
• Highly motivated to ensure transistors are developed meeting the required reliability standards
• You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues
• You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues

Minimum Qualifications:

• MS/PhD in Electrical Engineering or related field, PhD in Semiconductor Device Technology preferred
• 5 plus years industry experience in the field of CMOS device design, simulation, characterization
• Experience in developing advanced logic transistor technologies
• Experience in developing Analog FETs operating at higher Voltages
• Preferred: Experience in the field of High Voltage applications, reliability, characterization, device development
• Understanding of analog design concepts
• Good presentation skills
• Excellent team and mentoring skills

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

Description

As a NAND CMOS Process Integration Engineer in the Singapore Technology Development department at Micron Technology Inc., you will be responsible for developing 3D NAND CMOS devices scaling and enhancing their performance, reliability and manufacturability.

Responsibilities:

• Develop and innovate critical CMOS modules. Drive multi-functional teams to optimize existing process flows and develop new innovative solutions to meet product requirements and manufacturability.
• Develop/re-define critical specifications criteria for optimum product performance and drive activities to get them to manufacturing process capability.
• Extract and analyze inline, probe, parametric, reliability, and other critical metrics and predict future behavior of the CMOS device performance of the product to enable early innovative solutions to meet product and device specifications.
• Early introduction, characterization and validation of new CMOS device models and test structures for developing future NAND products.
• 3 dimensions analysis with the use of K2 view to extract layout information and combine with the doping profiles of each implant step for product development and integration solutions.
• Interact and collaborate with TCAD, modeling, and layout teams to drive clearer definition of CMOS device and reliability improvements across multiple tech-nodes and designs.
• Coordinate activities at manufacturing site towards gating experiment funding, conversions, and effectively communicate decisions made to all R&D, manufacturing, and relevant partners.
• Take on leadership role at quarterly yield summits and monthly program reviews in summarizing complex problems, deriving and explaining actions taken to address them and getting R&D, manufacturing, and senior management teams on the same page.
• Assist in the transfer of a new technology from R&D to manufacturing and contribute towards ensuring successful ramp and qualification. Supporting the transfer, documentation and training of module fundamentals into manufacturing.

Requirements:

• MS or PhD in Electrical Engineering preferably specialized in Microelectronics and Semiconductor Device Physics. Prior technology development and tech transfer/manufacturing experiences are preferred.
• Fresh MS/PhD candidates with knowledge of semiconductor process Integration, device physics and CMOS engineering.
• Direct fab experience with nonvolatile memories manufacturing, knowledge of TCAD, K2 view layout, and NAND product are highly desirable.
• Ability to develop a strong, holistic, end-to-end understanding of CMOS device and its related module on NAND technologies, related structural and electrical fail mechanisms.
• Deep understanding of probe failure mechanism, ability to do electrical bench data collection.
• Self-motivated, self-governing with proven ability to work in a demanding and dynamic environment.
• Experienced in coordinating cross-functional teams to achieve a goal.
• Solid data analysis, communication and reporting abilities with demonstrated presentation abilities.
• Curiosity and natural tendency of learning new things independently.
• Ability to travel for extended periods of time to the US for collaborative R&D work.

Working Location: Fab10, 1 North Coast Drive, Singapore 757432

Your responsibilities will include, but not limited to:

FAB PROCESS KNOWLEDGE

• Proficient knowledge of wafer process and traveler flows for main products.
• Understands high-level factory limitations.
• Knowledge of capacity analysis and production planning. Knowledge about Sales and Operations Planning (SNOP) and MOR business processes.

PROJECT MANAGEMENT

• Demonstrates advanced ability to successfully define, plan, and handle the implementation of complicated projects.
• Appropriate and timely escalation of roadblocks to project sponsor.
• Developing delegation, risk/cost analysis, and project tracking skills.
• Regular communication of project progress to stakeholders, team members and sponsors.

PLANNING SYSTEMS, APPLICATIONS, COMPUTER, MICROSOFT OFFICE and PROGRAMMING SKILLS

• Understands the interaction of planning systems and associated applications used within Micron.
• Understanding of system interaction, adept at extracting data from various systems.
• Demonstrates ability to use Microsoft Office to develop presentations, handle projects and perform all other tasks in an effective manner.
• Advanced ability in Excel and proficient in using VBA Macros to enhance and automate tasks.
• Advanced ability in Programming / Data Automation programs, e.g. Python, Tableau, Power BI, etc. to automate tasks and support data analysis.

STRATEGIC OPERATIONS

• Provide planning support for Emerging Projects.
• Support capacity studies for Special Projects.
• Provide Business Planning support for various Capacity Options.
• Analyze Fab Capital Expenditure and Output Scenarios for Business Plan.
• Fab Mix optimization for various Capacity and Capital Expenditure Scenarios.
• Efficient management of Capital Expenditure scenarios and cash flows through scenarios comparison and optimization.
• Ability to provide and evaluate modeling options that enable lowest cost of operation.

FINANCIAL ANALYSES

• Partner with Finance team to complete a thorough financial analysis through various scenarios (Manufacturing Cost, return on investment/payback, Net Present Value NPV, Profit/Loss (P/L) analysis).
• Ability to provide and evaluate Scenario options to improve financial analysis.

Requirements :

• Bachelors’ Degree in Industrial Engineering or equivalent experience. Additional major/minor in Computer Science, or a Business-related or quantitative field (Finance, Economics or similar subject area), MBA or Master’s degree is a plus
• Proficient in Microsoft Office to develop presentations, handle projects and perform all other tasks in an effective manner.
• Advanced ability in Excel and proficient in using VBA Macros to enhance and automate tasks.
• Advanced ability in Programming / Data Automation programs, e.g. Python, Tableau, Power BI, etc. to automate tasks and support data analysis.
• Ability to turn complex and ambiguous problem statements into structured solution.
• Experience analyzing and interpreting data, drawing conclusions, defining recommended actions, and reporting results cross diverse technical and non-technical groups
• Experience working independently in teams, establishing and maintaining multi-functional relationships
• Experience in a combination of capacity analysis, business analysis or process analysis is advantageous

Working Locations :

1, North Coast Drive, Singapore 757432

As the Facilities regional Water engineer, you will be responsible for leading water and waste water system design for construction projects, providing technical support, expertise, and lead business process alignment on operational and maintenance programs for all front and back end sites.  As a global team member residing in your current site/geography, you will represent all regional facility O&M alignment initiatives. You will also lead the design for construction team and incorporate critical operational and maintenance into design for construction projects. You will work with central team on critical metrics, include eliminating production events that minimize lost moves and scrap.

Responsibilities and tasks:

• Expert understanding of each sites UPW/WWT systems operational and maintenance capabilities in order to provide critical support.
• Leading UPW/WWT system design for construction projects
• In addition to your global water engineering role you will also provide site/regional support for global facility initiatives at your location.
• Technically lead a global cross functional team focused on operational excellence with the site systems engineers.
• Provide support to all sites including on site presence for critical failures.
• Actively involved in TPM implementation and alignment along with ongoing support
• Drive improvement in the quality of our utilities through variation reduction (SPC).
• Drive the alignment for common methodologies including SPC, conformance, SIPP’s, MOC and 8D problem solving throughout the network.
• Identify and deploy cost reduction efforts while optimizing and reducing energy usage for UPW/WWT systems throughout the network.
• Assess and insure effective and consistent PM and predictive maintenance programs, procedures and checklists across the network.
• Regular communication with the site engineering and O&M teams on status and performance.
• Analyze and benchmark equipment performance.
• Identify and develop training and certification programs that support global and site efforts
• Develop appropriate metrics to drive improvement (On time PM’s, MTTF, MTTR etc.).
• Send out regular updates with key items of focus and initiatives. 
  You will review FIPA/METS events and provide recommendations to drive the reduction of critical impact events.
• Collaborate with the construction / engineering team to insure alignment on projects.
• Review site sustaining capital requests in collaboration with construction/engineering.
• Support the network effort to implement, monitor and drive continuous improvement for success of Micron’s Sustainability programs in alignment with the long-term Sustainability strategy.
• Benchmark system performance and drive Best-In-Class approach (BICs) across network.
• Provide technical advice and support to overcome challenges and roadblocks in project planning & execution.
• Support sustainability projects achievement data acquisition and validation in central tracking depository.

Requirements:

• Excellent analytical and good decision making skills.
• Excellent interpersonal skills and demonstrated ability to communicate effectively at all levels within the organization.
• Excellent teamwork and collaboration with other groups, internally and externally.
• Proven ability to solve problems across multi-functional and multi-cultural groups within and outside facilities.
• Proven ability to multi-task and lead team to meet challenging deadlines and goals.
• Proven ability to continuously improve systems and processes.
• Ability to foster strong relationships from cross-functional and multi-cultural groups.
• Exceptional customer focus.

Education Required

• Bachelor’s Degree in Chemical/Mechanical Engineering

Experience required

• 10 years of Facilities  UPW/WWT or Chemical/Gas system engineering experience with minimum 6 years in semiconductor industry

Experience Desired

• Lead or actively involved in global facility engineering efforts

Responsibilities

Excellent execution on assembly process for 1st NPI success and smooth transfer process from NPI to HVM

• Excellent execution of the qualification of NPI products / packages build that proliferate from the pilot products and packages according to planned timeline
• Full responsible on support NPI business process with process TRA, POS, PFMEA/QCP, risk mitigation and documentations.
• Deliver BIC yield and cost on product NPI with integration of DFx BIC package solution, process guideline and design rules.
• Collaboration with multi-functional team from NPI to LVM/HVM process transfer. On-time execution of NPI Customer samples and Engineering Samples build for new products and packages

SME Process Owner Responsible for Continuous Improvement on Process Yield, Defect Elimination and Process Characterization

• Process owner to perform on-time detection with data analysis for process yield improvement. Lead the defect elimination and continue improvement action, with problem solving methodology, statistical analysis and integration solution decision.
• Process owner to develop process recipe for BIC UPH, conducting process characterization to define process parameters and boundary.
• Continuous develop in depth assembly process technical knowledge, well understand process capability/tolerance//spec limit/CpK, and apply key tools PFMEA/QCP/APC/FDC/Alarm on assembly processes Cz/Development/NPI.
• Global leader for cross team collaboration on network BKM, process recipe spec and recipe standardization/conversion.

Technology enablement and development – Process, Material, Equipment

• Participate and support Product Roadmap, to enable key process capability and technology development to ensure packaging solution is ready prior 1st Qual Silicon deliver.
• Frequent engagement with equipment and material supplier (at least interval of monthly or daily/weekly for process issues)
• Collaboration with Supplier and involvement Supplier Roadmap (Material/Equipment/OSAT), to understand market trends and competitor’s direction, ensure key process technology and capability enablement is in-line.
• Frequent review and participant Competitor Analysis, to understand market trends and competitor’s technology/capability boundary
• Engage and follow PDE business process (TGR, TORB, KEG interlock) for new technology qualification, alignment and safe launch

Teamwork and General expectation

• Trainer/Buddy/Mentor for new team members, build effective relationships within team and cross team (peers, counterpart)
• Regularly review data and direction with supervisor. Demonstrate sound data analysis and judgment. Present reports and findings with appropriate conclusions, recommendations and decision making.
• Develop, or coordinate development of, training materials for existing/new process
• Safety Identify and promptly report hazards, follow safety procedures and area work rules including proper PPE, lockout and chemical safety.

Qualification

• Bachelor or Masters in Electrical Engineering, Materials Science, Chemical Engineering, or related field. A PhD is a plus.
• 1-3 or more years of experience in Semiconductor Manufacturing, Process & Equipment Engineering and/or New Product Introduction.
• Demonstrated track record in baseline performance improvement, business process creation, process simulation techniques, data interpretation skills and proficiency in statistical analysis/method.
• Be able to comfortably work across organizational boundaries and geographies.
• Ability to effectively collaborate with multi-functional organizations to understand needs and translate them into actionable plans, deliverables, and resource requirements.
• Organized, meticulous, and strong focus on results.
• Excellent analytical skills
• Excellent communication and written skills

Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. Micron’s teams of dreamers, visionaries, and scientists have redefined innovation—designing and building some of the world’s most advanced memory and semiconductor technologies. Information Security Protection processes from within all business units with connectivity to corporate information security strategy is fundamental to protect Micron’s mission.

As the Frontend Manufacturing IP Security Engineer/Senior Engineer, you will be responsible to help transform how the corporate Cyber and Information security strategies connect and integrate into all Micron technology and business teams. You will work directly with local business unit information security teams to advocate and coordinate global security initiatives within the business areas, bring in real world security threat and awareness training campaigns, as well as leader or general population security awareness campaigns. A primary attribute of the role is to be the conduit for feedback between Global Security and Micron’s business area teams. Equally important is working with Frontend Manufacturing teams to internally assess and establish best practices within the business communities while bringing insights from local successes to a broader Micron community. With business and information knowledge, you will be a partner with Global Security and business leadership to create and enable Micron’s overall security strategy. In this, you will gain a broad perspective by working on a variety of information sources, control solutions, and dynamic business conditions across a global organization to analyze issues, make well-reasoned recommendations and solve problems to protect and enhance organizational value.

Responsibilities:
• Collaborate and conduit two-way interaction with Global Security Team and business areas supporting roadmaps, strategies, and requirements from both perspectives. Bridge security goals and commitments with articulated business needs driving towards a common set of goals and objectives

• Collaborate with IP site reps to create, advocate, and present across-the-business security campaigns, awareness, and cultural messaging. Assessments of security influence across Micron

• Partner with Global Security Team, BISO and Data Protection Community to develop associated processes and automation requirements to enable.

• Coordinate with experts on various topics to present and provide education around their areas of expertise. Create opportunities to increase security knowledge within the Data Security Community

• Establish and maintaining leading and lagging metrics to security problems, solutions, and business processes with stakeholders to enable a business facing dashboard support security strategies and needed efforts

• Provide coordination for the Data Protection Community and BISOs to drive best practices and creative solutions to data security problems. Drive to enable common guidance and goals (records and access management, unstructured data solutions, vendor and contractor access/data models)

• Partner with BISO representatives to drive best-known-methods within organizations supporting security culture and collaborate opportunity to expand

• Assess and manage exception approvals for all global operations

Qualifications:
• Must be able to understand and effectively communicate vision and technical concepts in appropriate terminology at all levels of the organization

• Ability to balance security with end user productivity and operational impacts in a large organization to provide transparent, secure solutions

• Strong Agile development knowledge, build in increments and iterate

• Excellent organizational skills and the ability to see solutions to their conclusion

• Ability to be self-directed and a fast learner and ability to gain understanding of new solutions

• A sense of urgency, prioritization, growth mindset and self-motivated personality

• Demonstrated ability to promote security practices and drive improvements into organization’s overall security framework

• Advantages with CISSP/CISM/CISA/ISO27001/PMP certification

Education & Experience:

• Bachelors/Masters degree in Engineering or Business Field, Computer Science, or Cyber security related field

• Equivalent experience in industry on Intellectual Property or Cyber Security

• Understanding of information technology general controls, process and structure

• Proven communication skills with cross-functional teams

• Strong skills in decision-making, prioritization and problem solving

• Strong skills in Project management and organization change management

Working Location :

1, North Coast Ave, Singapore 757432

Analyzes risk to business activities and operations. Identifies areas of potential loss or damage for current and proposed business and financial operations, processes, structures and cyber-risk exposure and quantifies impact. Implements and evaluates compliance with business and cyber risk-reduction policies, processes and standards. May participate in the development and maintenance of disaster recovery and business continuity plans. Supports organizational processes and programs for mitigation of financial risk, including administration of insurance. May support and administer security and health/safety programs in addition to risk management activities.

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities
• Install equipment and/or CIP hardware for evaluation by the process development team to enable early introduction, maturity, and adoption for current and next node of 3D NAND technology.
• Work with the Fab layout and facility team to ensure smooth and on time installation and operation of the equipment.
• Work with process development team to quantify benefits of equipment/CIP hardware.
• Develop and optimize existing equipment hardware to meet the productivity requirements of advanced 3D NAND parts.
• Participate with Boise TD equipment development peers on technology choices for the upcoming nodes and able to translate future technology needs into clear equipment requirements.
• Identify disruptive equipment early, work with manufacturing and Boise TD to identify viable evaluation path forward in manufacturing.
• Design and implement advanced equipment monitoring and control methodologies.
• Lead team or sites or suppliers on complex projects in focused meetings with end goal of maturity an equipment technology in record times for technical advantage, cost and productivity.
• Serve as a technical expert within Micron, provide advice and recommendations to senior management on improvements from equipment development. Lead and initiate innovation projects through patents/technical papers.
• Identify and resolve safety hazards; follow safety procedures including lockout, chemical safety, lifting techniques and ergonomically correct methods.

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above
Location: Fab10N
Closing Date: Until filled

As a NAND CMOS Device Engineer, you will help set the direction for current and future CMOS technology for Micron’s NAND Memory Technology Roadmap!

You will work with the Design Team to set electrical targets and define transistor structures to meet these targets. You will guide the device technology development and be in close relation with Process Integration, Design Engineering, Design, Design Rules, Reliability, Transistor Modeling, TCAD (Technology Computer-Aided Design), and Parametric Test, to name a few! In addition, you will ensure that the developed technology is manufacturable and highly yielding and that these considerations are designed into the technology from the start.

Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps

• You give directions on how to improve our device portfolio, both in performance and cost effectiveness
• You define, execute, and analyze silicon experiments for future device generations
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules
• Work with TCAD simulation group to develop strategies for transistor structures to meet targets
• You strive to ensure that transistor models are correctly targeted to anticipate final silicon
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring
• Highly motivated to ensure transistors are developed meeting the required reliability standards
• You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues
• You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues

Minimum Qualifications:

• MS/PhD in Electrical Engineering or related field, PhD in Semiconductor Device Technology preferred
• 5 plus years industry experience in the field of CMOS device design, simulation, characterization
• Experience in developing advanced logic transistor technologies
• Experience in developing Analog FETs operating at higher Voltages
• Preferred: Experience in the field of High Voltage applications, reliability, characterization, device development
• Understanding of analog design concepts
• Good presentation skills
• Excellent team and mentoring skills

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities
• Install equipment and/or CIP hardware for evaluation by the process development team to enable early introduction, maturity, and adoption for current and next node of 3D NAND technology.
• Work with the Fab layout and facility team to ensure smooth and on time installation and operation of the equipment.
• Work with process development team to quantify benefits of equipment/CIP hardware.
• Develop and optimize existing equipment hardware to meet the productivity requirements of advanced 3D NAND parts.
• Participate with Boise TD equipment development peers on technology choices for the upcoming nodes and able to translate future technology needs into clear equipment requirements.
• Identify disruptive equipment early, work with manufacturing and Boise TD to identify viable evaluation path forward in manufacturing.
• Design and implement advanced equipment monitoring and control methodologies.
• Lead team or sites or suppliers on complex projects in focused meetings with end goal of maturity an equipment technology in record times for technical advantage, cost and productivity.
• Serve as a technical expert within Micron, provide advice and recommendations to senior management on improvements from equipment development. Lead and initiate innovation projects through patents/technical papers.
• Identify and resolve safety hazards; follow safety procedures including lockout, chemical safety, lifting techniques and ergonomically correct methods.

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above

Location: Fab10N

Closing Date: Until filled

As a NAND CMOS Device Engineer, you will help set the direction for current and future CMOS technology for Micron’s NAND Memory Technology Roadmap!

You will work with the Design Team to set electrical targets and define transistor structures to meet these targets. You will guide the device technology development and be in close relation with Process Integration, Design Engineering, Design, Design Rules, Reliability, Transistor Modeling, TCAD (Technology Computer-Aided Design), and Parametric Test, to name a few! In addition, you will ensure that the developed technology is manufacturable and highly yielding and that these considerations are designed into the technology from the start.

Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps

• You give directions on how to improve our device portfolio, both in performance and cost effectiveness
• You define, execute, and analyze silicon experiments for future device generations
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules
• Work with TCAD simulation group to develop strategies for transistor structures to meet targets
• You strive to ensure that transistor models are correctly targeted to anticipate final silicon
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring
• Highly motivated to ensure transistors are developed meeting the required reliability standards
• You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues
• You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues

Minimum Qualifications:

• MS/PhD in Electrical Engineering or related field, PhD in Semiconductor Device Technology preferred
• 5 plus years industry experience in the field of CMOS device design, simulation, characterization
• Experience in developing advanced logic transistor technologies
• Experience in developing Analog FETs operating at higher Voltages
• Preferred: Experience in the field of High Voltage applications, reliability, characterization, device development
• Understanding of analog design concepts
• Good presentation skills
• Excellent team and mentoring skills

Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Involvement may begin at any step from pilot plant to full-scale manufacturing. Coordinates design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compiles and evaluates test data to determine appropriate limits and variables for process or material specifications. May conceive and plan projects involving definition and selection of new concepts, equipment automation technology, and approaches in the processing or development of new or improved processes.

As a Senior Equipment Engineer/Equipment Engineer in the NTI, you will be expected to support R&D activities associated with rapid deployment of First-of-Kind equipment, the CIP hardware evaluations and managing on the timeline needed to deploy in current technode/next advance technode on time. Good team spirit and good collaborations working is needed with various stakeholders including (not limited to) facilities/fab support/Gas & Chemical/EHS/F4/F10/Central team etc with various equipment setup and improvement work necessitated thereof as well as to ensure extended engagement with F4 on the upcoming First-of-Kind equipment in upcoming technode. Expected to work independently with minimal direction and complete projects in a timely manner and achieve set objectives.

Responsibilities
• Install equipment and/or CIP hardware for evaluation by the process development team to enable early introduction, maturity, and adoption for current and next node of 3D NAND technology.
• Work with the Fab layout and facility team to ensure smooth and on time installation and operation of the equipment.
• Work with process development team to quantify benefits of equipment/CIP hardware.
• Develop and optimize existing equipment hardware to meet the productivity requirements of advanced 3D NAND parts.
• Participate with Boise TD equipment development peers on technology choices for the upcoming nodes and able to translate future technology needs into clear equipment requirements.
• Identify disruptive equipment early, work with manufacturing and Boise TD to identify viable evaluation path forward in manufacturing.
• Design and implement advanced equipment monitoring and control methodologies.
• Lead team or sites or suppliers on complex projects in focused meetings with end goal of maturity an equipment technology in record times for technical advantage, cost and productivity.
• Serve as a technical expert within Micron, provide advice and recommendations to senior management on improvements from equipment development. Lead and initiate innovation projects through patents/technical papers.
• Identify and resolve safety hazards; follow safety procedures including lockout, chemical safety, lifting techniques and ergonomically correct methods.

Requirements:
• A minimum of 2-3 years of experience in the semiconductor industry in the area of equipment engineer roles.
• In-depth understanding of the equipment operation, working principles, troubleshooting and tool installation procedure is a must.
• Exposure to R&D equipment transfer and ability to develop/optimize equipment hardware design is preferred.
• Communications and collaboration with partners both locally and globally. Strict adherence to Micron Intellectual Property protection policy is a must.
• Self-motivated and adaptable to Micron’s fast paced, demanding and dynamic work environment; flexibility to work for extended hours, as required.
• Excellent oral and written communication skills with ability to convey the message clearly and sharply both locally and globally.
• Excellent ability to prioritize and manage multiple projects simultaneously; efficiently utilize available resources or seek peers’ and/or management help to get over the roadblocks to drive to solutions.
• Encourage and enforce safe, compliant behavior through periodic communications and the performance management process.

GJS for this position: E2 and above
Location: Fab10N
Closing Date: Until filled

Advance Packaging Integration – Senior Engineer (Package Development Engineering, Silicon Technology Package Integration) (PDE STPI)

We are looking for a Package Silicon Integrator in Package Development Engineering (PDE) Senior Engineer who will lead and drive Micron’s Packaging Technology Development Projects meeting Time to Market (TTM) business unit needs as well as meeting performance targets for Thermal, Electrical, Mechanical, Reliability and Cost. You will collaborate with Micron’s multi-functional team that include Product Development, Wafer level process, Assembly, Test, Manufacturing and Global Quality. Together, we will be responsible for the designing Test Vehicle Development Strategy, and execution to definition, development, and delivery of state-of-the-art product/packages that will shape the future of advanced computing, automotive and mobile products.

Responsibilities will include, but are not limited to:

• Drive package technology integration activities for the silicon test chip development projects and support NPIs to keep roadmap items on track to meet “go to market” timelines.
• Coordinate core team in Development and NPI space of advanced 2.5D/3D packages and standard packaging to drive material and BOM choices, body sizes, manufacturability, and package constructions to achieve acceptable Design for Manufacturing (DFM) and Design for Reliability (DFR) requirements.
• Evaluate wafer design inclusive of bondpad, scribe, pillars/bump and polyimide, and drive materials and BOM choices such as die thickness and mold compound to meet chip package interaction requirements.
• Drive materials characterization from both package and die components to understand chip package interaction mechanism using TMA, DMA, nanoindentation, and packaging mechanical and thermal stress stimulus.
• Drive novel solutions with silicon design and product teams to recommend the optimum package solutions to meet electrical, mechanical (1st, 2nd, and 3rd level interconnect), thermal, reliability, cost, and other system level requirements.
• Interface closely with multi-functional team that include Product Development, Wafer Level Process, Assembly, Test, Manufacturing and Global Quality and manage the product/package to mass production.

Requirements:

• Bachelor/Masters of Science in physics, materials, mechanical, chemical, or electrical engineering. MS or PhD preferred
• 5+ years of relevant experience in semiconductor manufacturing or a related field, with hands-on experience in semiconductor packaging or Frontend processes, specifically in technology on
• Appreciation for Structured Problem Solving
• Ability to interpret die-, package-, and system-level design and simulation (thermal/mechanical/electrical) methodologies and results
• Knowledge in Chip Package Interaction (CPI)
• Experience and working knowledge with 2.5D/3D heterogeneous integration technologies such as WLFO, SoIC, CoWoS, WoW, InFO, and other chiplet/SiP architectures is a plus
• Experience with wafer bumping, package assembly, substrate technology, BOM selection, testing and product development lifecycle
• Excellent communication skills with the ability to convey complex technical concepts to both technical and non-technical partners
• Demonstrated leadership experience in guiding multi-functional teams and driving technical excellence

Keen on the role? Apply now!

Advance Packaging Integration – Senior Engineer (Package Development Engineering, Silicon Technology Package Integration) (PDE STPI)

We are looking for a Package Silicon Integrator in Package Development Engineering (PDE) Senior Engineer who will lead and drive Micron’s Packaging Technology Development Projects meeting Time to Market (TTM) business unit needs as well as meeting performance targets for Thermal, Electrical, Mechanical, Reliability and Cost. You will collaborate with Micron’s multi-functional team that include Product Development, Wafer level process, Assembly, Test, Manufacturing and Global Quality. Together, we will be responsible for the designing Test Vehicle Development Strategy, and execution to definition, development, and delivery of state-of-the-art product/packages that will shape the future of advanced computing, automotive and mobile products.

Responsibilities will include, but are not limited to:

• Drive package technology integration activities for the silicon test chip development projects and support NPIs to keep roadmap items on track to meet “go to market” timelines.
• Coordinate core team in Development and NPI space of advanced 2.5D/3D packages and standard packaging to drive material and BOM choices, body sizes, manufacturability, and package constructions to achieve acceptable Design for Manufacturing (DFM) and Design for Reliability (DFR) requirements.
• Evaluate wafer design inclusive of bondpad, scribe, pillars/bump and polyimide, and drive materials and BOM choices such as die thickness and mold compound to meet chip package interaction requirements.
• Drive materials characterization from both package and die components to understand chip package interaction mechanism using TMA, DMA, nanoindentation, and packaging mechanical and thermal stress stimulus.
• Drive novel solutions with silicon design and product teams to recommend the optimum package solutions to meet electrical, mechanical (1st, 2nd, and 3rd level interconnect), thermal, reliability, cost, and other system level requirements.
• Interface closely with multi-functional team that include Product Development, Wafer Level Process, Assembly, Test, Manufacturing and Global Quality and manage the product/package to mass production.

Requirements:

• Bachelor/Masters of Science in physics, materials, mechanical, chemical, or electrical engineering. MS or PhD preferred
• 5+ years of relevant experience in semiconductor manufacturing or a related field, with hands-on experience in semiconductor packaging or Frontend processes, specifically in technology on
• Appreciation for Structured Problem Solving
• Ability to interpret die-, package-, and system-level design and simulation (thermal/mechanical/electrical) methodologies and results
• Knowledge in Chip Package Interaction (CPI)
• Experience and working knowledge with 2.5D/3D heterogeneous integration technologies such as WLFO, SoIC, CoWoS, WoW, InFO, and other chiplet/SiP architectures is a plus
• Experience with wafer bumping, package assembly, substrate technology, BOM selection, testing and product development lifecycle
• Excellent communication skills with the ability to convey complex technical concepts to both technical and non-technical partners
• Demonstrated leadership experience in guiding multi-functional teams and driving technical excellence

Keen on the role? Apply now!

Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.  Micron’s teams of dreamers, visionaries, and scientists have redefined innovation—designing and building some of the world’s most advanced memory and semiconductor technologies.  Information Security Protection processes from within all business units with connectivity to corporate information security strategy is fundamental to protect Micron’s mission.

As the Frontend Manufacturing IP Security Manager/Principal Engineer, you will be responsible to help transform how the corporate Cyber and Information security strategies connect and integrate into all Micron technology and business teams.  You will work directly with local business unit information security teams to advocate and coordinate global security initiatives within the business areas, bring in real world security threat and awareness training campaigns, as well as leader or general population security awareness campaigns.  A primary attribute of the role is to be the conduit for feedback between Global Security and Micron’s business area teams.  Equally important is working with Frontend Manufacturing teams to internally assess and establish best practices within the business communities while bringing insights from local successes to a broader Micron community.  With business and information knowledge, you will be a partner with Global Security and business leadership to create and enable Micron’s overall security strategy.  In this, you will gain a broad perspective by working on a variety of information sources, control solutions, and dynamic business conditions across a global organization to analyze issues, make well-reasoned recommendations and solve problems to protect and enhance organizational value.

Responsibilities:
• Collaborate and conduit two-way interaction with Global Security Team and business areas supporting roadmaps, strategies, and requirements from both perspectives. Bridge security goals and commitments with articulated business needs driving towards a common set of goals and objectives

• Define clear goals and strategic initiatives to create, advocate, and present across-the-business security campaigns, awareness, and cultural messaging.  Assessments of security influence across Micron

• Understand and lead efforts to meet the requirements of internal and external customers. with Global Security Team, BISO and Data Protection Community to develop associated processes and automation requirements to enable.

• Coordinate with experts on various topics to present and provide education around their areas of expertise.  Create opportunities to increase security knowledge within the Data Security Community

• Coordinate leading and lagging metrics and to security problems, solutions, and business processes.  Partner to enable a business facing dashboard support security strategies and needed efforts

• Provide coordination for the Data Protection Community and BISOs to drive best practices and creative solutions to data security problems.  Drive to enable common guidance and goals (records and access management, unstructured data solutions, vendor and contractor access/data models)

• Partner with BISO representatives to drive best-known-methods within organizations supporting security culture and collaborate opportunity to expand

• Handle escalations and exception approvals for all Global Operations

Requirements :
• Ability to understand and effectively communicate vision and technical concepts in appropriate terminology at all levels of the organization

• Ability to balance security with end user productivity and operational impacts in a large organization to provide transparent, secure solutions

• Strong Agile development knowledge, build in increments and iterate

• Excellent organizational skills and the ability to see solutions to their conclusion

• Ability to be self-directed and a fast learner and ability to gain understanding of new solutions

• A sense of urgency, prioritization, and growth mindset

• Demonstrated ability to promote security practices and drive improvements into organization’s overall security framework

• Advantages with CISSP/CISM/CISA/ISO27001/PMP certification

Education & Experience:

• Bachelors/Masters degree in Engineering or Business Field, Computer Science, or Cyber security related field

• Equivalent experience in industry on Intellectual Property or Cyber Security

• Understanding of information technology general controls, process and structure

• Proven communication skills with multi-functional leaders

• Strong skills in decision-making, prioritization and problem solving

• Strong skills in Project management and organization change management

Identifies, analyzes, monitors and minimizes areas of risk that pertain to information technology. Coordinates closely with the disaster recovery and data security disciplines; all three disciplines (risk management, disaster recovery and data security) may be part of the same department.

Job Responsibilities :

• Enhance Probe’s capability to perform real-time reporting, monitoring and flagging of Production issues using Tableau & customized software solutions
• Develop innovative software solutions for Engineering & Production teams to reduce turn-around time in resolving issues
• Implement code to automate material tracking, product disposition & validation to ensure high-quality products for end-customers
• Collaborate with the worldwide Probe community on projects with significant impact to Probe

Job Requirements :

Education

• Bachelor’s degree in Electronic Engineering, Computer Engineering, Computer Science or equivalent combination of education and experience is preferred

Experience, Skills, Knowledge and Abilities

• Candidates with strong grasp of C, Perl, Linux, SQL, Tableau skills preferred
• Excellent written and verbal communication skills
• Proven ability to handle multiple priorities at once and stay focus on critical issues
• Successfully demonstrated teamwork skills with a strong focus on effective team dynamics
• Strong problem solving skills and the ability to conduct root cause analysis and elimination
• Solid technical judgment with good analytical and problem solving skills
• Proven ability to deliver results while working under pressure

As a member of the HIG HBM Media Health HVM team you will lead and develop a high-performing products driving Media Health Manufacturing and activities within the HBM Product and Systems Engineering Team. You will lead a portfolio of Best-In-Class Next Generation HBM Product focused on the critical KPI’s Quality, Cost, Cycle Time and Scale. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization.

Key Responsibilities

• Optimized Test Coverage: The responsibility of ensuring optimized test coverage on all current and future HIG HBM design architectures and process nodes is a technical aspect of this role. This is crucial for maintaining the effectiveness and efficiency in high-volume manufacturing.
• Promotion of Innovation: The role involves promoting innovation and driving for changes that will provide Micron with a technical advantage over its competition. This is vital for maintaining Micron’s competitive edge in the market.
• Product Development and Validation: This role is pivotal in developing, validating, characterizing, and qualifying Micron’s next-generation HBM products. Ensuring that these products are reliable and meet the necessary standards is a technical task that directly impacts the market readiness of the products.
• Support for New Product Design Validation: The role provides support for design verification and in-depth circuit of new products using CAD tools and Verilog simulations. This technical support is crucial for the development of new products and technologies.
• Yield Improvement and Cost Reduction: The role involves technical tasks like improving manufacturing test yields (Specifically related to Device Issues from the DRAM, Interface and Stacked Die Yield), reducing test time, and resolving yield-related issues. These activities are critical for cost reduction and meeting yield targets.
• Root Cause and Resolution of Qual and RMA Device Issues.
• Process Conversions and HVM: The role involves providing recommendation to fab teams for new process conversions to reduce cost, increase yields. This is critical as it directly impacts the yield, quality, reliability, and performance of NAND products, which are key components in many modern technologies.
• Risk Management: The role requires communication with Product Managers/Leads to manage risks associated with DPM process conversions. This is crucial in ensuring that the conversions move at an appropriate pace, balancing the need for innovation with the need for stability and reliability.
• Project Management: Developing project management skills within the team ensures efficient execution of projects, leading to timely delivery of technological solutions.
• Technical Decision Making: The role involves making final decisions on risk analysis and project prioritization. These decisions directly impact the direction of technological development.
• Cross-Functional Collaboration: This role necessitates collaboration with various cross-functional teams such as Fab, HBM Technology Development, HBM Design, System Development, and Quality/Reliability team. This collaboration is vital for the holistic development and shipping of end products.

Requirements

• Bachelors/Masters Electrical Engineering Degree with at least 1 year of experience in the semiconductor industry.
• Experience in CMOS device design, simulation, characterization and development of Analog/CMOS transistors operating at higher Voltages.
• Programming skills/experience in Python; logic gate and transistor operation knowledge; circuit simulation or circuit debug skills/experience.
• Dedicated and highly motivated with a flexible approach towards adapting to different roles in a dynamic working environment (from leading the team to leading technical programs).
• Proven track record of collaborative work within/across teams to address sophisticated business and engineering problems.
• Strong sense of responsibility and accountability towards assigned role with professional work ethic.
• Work on site in Singapore with international travel to USA, Taiwan and Japan.

As a Non-Volatile Memory Quality & Reliability Assurance (NVMQRA) Engineer at Micron Technology, you will be responsible for performing formal Failure Analysis of customer reported failing devices via the Returned Material Authorization (RMA) process. You will be required to summarize lab analysis results at the electrical and physical level to identify root cause and establish an associated containment plan. In this role, you will have the opportunities to collaborate with various engineering and manufacturing stakeholders to evaluate and review Corrective Actions /Preventive Actions. You will provide documentation of the RMA findings and oversee the final customer report till closure. In addition, for the senior role, you will be asked to provide guidance and lead the team when solving complex unplanned deviations reported by our customers. Project management skills are necessary and the ability to make critical decisions that directly translate to quality and timely completion of the project is highly desirable. You will also be required to spearhead the sustaining efforts and keeping up to date on new product knowledge, as well as developing and mentoring new talents.

Responsibilities and Tasks

Perform Failure Analysis of Customer Returns

• Understand customer complaint of the memory component failure
• Initiate communication with Micron Customer-facing team for further details on customer complaint, requesting additional questions to provide best opportunity for successful analysis
• Perform bench level analysis including initial data image analyis/examination
• Perform Automated Test Equipment (ATE) analysis and interpret results
• Work with the appropriate engineering teams (e.g., PE, PYE) to perform detailed fault isolation when electrical failure has been confirmed
• Summarize findings and submit for physical failure analysis (PFA).

Provide FA Reports for Micron Customer Facing Team for Communication to External Customers

• Summarize analysis at electrical and physical level into customer friendly formats.
• Work with the appropriate manufacturing Global Quality teams through the appropriate request systems (example: GPSS) for Root Cause and/or Corrective Action and a containment plan
• Identify potential risk to external customers
• Communicate with respective BU (Business Unit) on potential impact to customers
• Communicate FA updates through interim reports or during scheduled meetings with the customers.
• Provide formal FA Report with findings

Sustain Knowledge of Device Capabilities and Characteristics

• Keep up to date with latest Fab/ASM process technology
• Understand datasheet specifications for each device and the differences from previous technode for NOR * NAND product family
• Comprehension of qualification data and potential impact to customer operation
• Stay up-to-date on common customer applications and usage model
• Partnering with customer support team to resolve ongoing customer issues

Qualifications and Experience

• Excellent verbal and written communication skills in English. The ability to communicate clearly and concisely both verbally and in writing is critical in this role.
• Good organization skills and ability to multitask and coordinate between multiple issue at any given time.
• Ability to work effectively in cross-functional teams and handle pressure situations in a professional manner
• Excellent problem-solving and analytical skills with strong attention to details.
• Familiarity with NexTest /Teradyne bench analytical tools, scripting in linux console will be an added advantage.

Candidates with 2-3 years of experience in the semiconductor industry as Product or QA engineer are preferred. Relevant experienced candidates will be considered for the Senior Role.

Education

A Bachelor or Masters Degree in Electrical Engineering or similar field of study.