Position Overview:

The Senior/Staff Design Engineer will be responsible for developing micro-architecture for ISP and CV related algorithms, utilizing RTL design using Verilog/System Verilog coding and HLS tools like Catapult. They will analyze metrics such as power, performance, and area to meet key objectives, collaborate with architects and DV Engineersfor efficient verification signoff, and support FPGA tasks such as emulation,validation, and debugging.

Responsibilities:

• Develop micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Analyze and optimize metrics like power, performance, and area.
• Cooperate with verification architects and DV engineers to ensure high quality IP delivery.
• Support backend team for SoC signoff.
• Oversee FPGA tasks including emulation, validation, and debugging.

Qualification/Requirements:

• Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
• Experience: Minimum 5yearsand aboveof experience in ASIC design. Expertise in image signal processing projects is beneficial.
• Technical Skills:
• - Advanced proficiency in HDL languages (Verilog, System Verilog).
• - In-depth knowledge of all phases of ASIC frontend design and sign-off.
• - Extensive experience in image/vision/video data processing or algorithm acceleration.
• - Proficiency in scripting languages like Python, Perl, or C/C++.
• Soft Skills: Excellent leadership, teamwork, and communication skills.
• Additional Notes:Stronganalytical skills and the ability to lead complex projects independently and within teams.

As part of IME Integrated Circuit Design and System Department, we are seeking a candidate with relevant experience in analog integrated circuit design. This candidate will contribute to developing analog circuit blocks e.g. low-power operational amplifiers, voltage/current references, and voltage regulators based on thorough topology analysis. This candidate will work closely with other team members for the circuit design, test verification, as well as system integration and validation for a broad range of innovative sensor systems.

Role & Responsibilities

• Circuit schematic design and simulation, layout supervision, pre-tapeout design verification, test plan development and chip measurement
• Work together with teams to investigate novel circuit/system solutions to create new inventions

Requirements

• Bachelor’s / Master’s degree in Electronic Engineering
• Good understanding of CMOS analog IC design methodologies
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

As part of IME Integrated Circuit Design and System Department, we are seeking a candidate with relevant experience in analog integrated circuit design. This candidate will have the opportunity to develop unconventional ultrasound transducer drivers, receiver circuits for IoT and biomedical applications as well as cutting-edge high-speed analog circuits for advanced optical communication.

Role & Responsibilities

• Design and tapeout circuit blocks e.g. high linearity low-noise amplifier, variable gain amplifier, envelop detector, and high voltage driver for MEMS ultrasound transducers.
• Work together with team on system integration and demonstration.
• Work together with team to investigate novel circuit/system solutions to create new inventions.

Requirements

• Master’s / PhD degree in Electrical Engineering or equivalent
• Minimum 2 years of transistor-level analog circuit design experience
• Good understanding of CMOS analog IC design methodologies and successful tapeout experience
• Familiar with analog IC design and verification flow
• Design experience with high voltage BCD process would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

This is an opportunity to be a key player at a company with a great reputation in IoT semiconductor technology and growing business. We are looking for experienced/senior engineers to join our team in Singapore and be involved to develop the next generation IoT/AI chips based on a revolutionary architecture.

1. Work with team to define the design of WIFI/BT related modules.
2. Develop RTL design of one or more blocks, define RTL module partition, timing requirement etc.
3. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
4. Assist with the development of company documentation and generation of patents.

Qualification

1. Master's degree in Electrical Engineering (or equivalent), with 5+ years’ industry experience.
2. Team player, with good problem solving and communication skills.
3. Proficiency in System Verilog for RTL logic design and verification.
4. Familiarity with the design of digital MAC/baseband/high-speed interface/CPU or DSP is a plus.
5. Experience in Architecture/Block definition for SOC system such as WiFi, Bluetooth and GNSS.
6. Experience in micro-architecture design, and RTL coding with Verilog, familiar with Cadence and Synopsis tools.
7. Experience in synthesis, with analysis of power, timing and area.
8. Review micro-architecture to meet specification requirements and perform Design Quality Check
9. Experience in RTL and gate level simulation, unit test, system test and EDA verification

At Mediatek’s Memory Design Automation team, we work seamlessly with worldwide memory design team to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

Responsibility

1. Responsible for cutting edge technology node’s SRAM compiler design and deliver best quality of design kit.
2. Seamlessly collaborate with SRAM design and layout team to achieve highest quality of design kit delivery.
3. Responsible for data analysis and platform development of memory usage big data.
4. Responsible for physical verification (DRC/ERC/LVS/ANT/PERC) on SRAM compiler.
5. Responsible for spice simulation on timing, power and noise on SRAM compiler.
6. Responsible for QA check and development on SRAM compiler.

Requirements

1. Bachelor or Master Degree in Electrical and Electronic Engineering or Computer Engineering or Computer Science.
2. Multi-task capability and strong self-driven characteristics to meet challenging schedule.
3. Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
4. Strong interpersonal skills to work with team members with multi-cultural environment
5. Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
6. Candidate with experience is preferable.

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Mediatek’s Memory Design Automation team is looking for fresh talent to join us as a modeling engineer for the development of behavioral, FPGA, timing and DFT simulation models. The role will be required to create, debug and optimize SRAM models for ASIC design flow.

The candidate must be a team player, able to communicate clearly and concisely to deliver quality work on time.

About the team:

The Mediatek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness.

What you do:

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.

What you bring:

• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related discipline with at least 3 years of semiconductor industry experience.
• Have at least 3 years experience using Linux systems.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required
• Experience with EDA tools will be helpful:

o DFT: Logicvision, Tessent, Fastscan

o Synthesis: Design compiler, Genus

o Simulation tools:VCS, QuestaSim, NC

o STA tools such as PrimeTime

• Good scripting and flow automation skills, in Perl or Python.
• A team player, meticulous, able to work and learn independently are important attributes for this job.

Location: One North, Singapore

As part of IME Integrated Circuit Design and System Department, we are looking for a candidate with relevant experience in ultrasound imaging system design. This candidate will define an ultrasound transducer array beamformer IC architecture for imaging applications. The candidate will work closely with MEMS team on system architecture, circuit design, simulation, validation, and integration.

Role & Responsibilities

• Perform system-level beamformer architecture, design, and simulation, to derive circuit-level design specifications.
• Beamforming array optimization using AI algorithms.
• Design and implementation of beamformer algorithm in hardware.
• Work together with team to investigate novel circuit/system solutions to create new inventions.

Requirements

• Master’s / PhD degree in Electrical Engineering or equivalent
• Good understanding of ultrasound imaging systems and beamforming theories.
• Knowledge of AI algorithms and implementation will be a plus
• Familiar with IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

As part of IME Integrated Circuit Design and System Department, we are seeking a candidate with relevant experience in analog integrated circuit design. This candidate will contribute to developing analog circuit blocks e.g. low-power operational amplifiers, voltage/current references, and voltage regulators based on thorough topology analysis. This candidate will work closely with other team members for the circuit design, test verification, as well as system integration and validation for a broad range of innovative sensor systems.

Role & Responsibilities

• Circuit schematic design and simulation, layout supervision, pre-tapeout design verification, test plan development and chip measurement
• Work together with teams to investigate novel circuit/system solutions to create new inventions

Requirements

• Bachelor’s / Master’s degree in Electronic Engineering
• Good understanding of CMOS analog IC design methodologies
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. of 8 years of relevant verification experiences.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

On behalf of the hiring company that is in the Built Environment OEM space, we are looking for suitable personnel to join them as Software Development Executives (electrical background):

Responsibilities :

• Software Design: Develop software for various vertical transportation systems, including Housing & Development Board (HDB), private, and modernisation systems. Refer to approved layout drawings, production requests, machine applications, client specifications, and electrical straight diagram drawings.
• Electrical Diagram Review: Interpret and verify electrical straight diagram drawings from the Hardware Design Department. Identify and report any inconsistencies or errors.
• Documentation and Communication: Issue notices, instructions, software documents, and contract-related materials as needed.
• Factory Support: Assist factory testing staff with job software design and technical troubleshooting during system testing.
• Design Optimisation: Ensure that software designs are cost-effective and fully comply with client specifications and project timelines.
• Error Investigation: Participate in investigating software errors and develop corrective and preventive measures. Collaborate with the Electrical Department to address any discrepancies between software and hardware designs and resolve issues before shipping the system to the site.
• Field Support: Assist system installation staff during on-site installations. Troubleshoot problems, and modify software as necessary to meet client requirements.

Requirements

• A diploma (at least 3 years) or degree in Electrical Engineering
• Familiar with programming languages such as C, C++, etc
• Familiar with schematic or single-line designs/drawings
• Able to work independently and as a team

Remuneration will be pegged to qualification and experience

Location: East (near to MRT station)

EA Licence : 22C0971 | EA Registration : R21101298

Interested applicants are invited to apply directly at the NUS Career Portal

Your application will be processed only if you apply via NUS Career Portal

We regret that only shortlisted candidates will be notified.

Job Description

Research Area: Design for an aging population.

The research associate is expected to have solid understanding of the physical and mental capabilities of elderly citizens. The task will be to determine the most important areas of physical and mental degradation that affect the quality of lives of elderly citizens as well as the remedies that have been designed to address these areas of degradation.

Qualifications

The researcher needs to have a Masters' degree with at least 2 years' relevant experience, in physiotherapy, public health, bio-medical sciences (including bio-mechanical engineering).

ROLE:
IME is leading the effort to establish the industry leading Silicon Carbide R&D program. This program aims to advance 200mm Silicon Carbide technologies in various areas, such as epitaxy, device design, process integration & fabrication, and power module packaging. The main objective is to drive disruptive innovations in power device research, with a specific focus on >1.2KV power MOSFETs. These innovations are intended to enhance automotive technologies, vehicle electrification, safety measures, sustainable energy grids, and industrial automation. Key aspects to demonstrate for this role include high power device design, novel device concepts, doping design, gate oxidation, and wide-bandgap process simulations. To achieve this, we are seeking individual with extensive industry experience in using Synopsys/Silvaco TCAD simulator, relevant device characterization skills, design simulation development abilities, a willingness to mentor junior staffs, and strong interpersonal skills. The candidate will contribute to the wide-bandgap & Silicon Carbide team by utilizing their device knowledge, guiding team on device characterization, implementing state-of-art Silicon Carbide power MOSFETs (Planar, Trench & Super-Junction), and innovative novel power MOSFETs for future applications.

RESPONSIBILITIES:

• TCAD modeling & simulation, novel high power device design, simulation, and device characterization

• Design and simulate high voltage Silicon Carbide MOSFETs (planar, trench, SJ MOSFET, IGBT) with a blocking voltage of >1.2K using Synopsys/Silvaco simulator

• Design & simulate practical and effective junction terminations

• Provide guidances on device structure, optimizing cell, power/performance analysis, process risk assessment, and recommendations for experimental split and improvement

• Develop and apply fundamental MOS device physics-based TCAD modelling & electric field management to calculate band structure, carrier transport, blocking voltage,
switching properties, and thermal management for vertical power devices in the presence of interface state density, gate oxide defects, and defects in Silicon Carbide

• Model transport and carrier scattering in devices operating in extreme ambient conditions

• Collaborate with diverse teams, including process integration, characterization, and circuit design engineers, to analyze and troubleshoot device-related issues during
development

• Serve as a resource for colleagues with less experience, and lead small projects with manageable risks and resource requirements

• Work closely with both internal and external customers to understand customer issues and align their demands. And grow this wide-bandgap team to ~5 headcounts in the
next 3 years.

JOB REQUIREMENTS:

• PhD in Electrical Engineering or related field

• >10 years industrial experience for high power device design and modeling

• Deep knowledge of high voltage, high power MOSFETs (including Planar, Trench, S-J MOSFETs, and IGBTs) design and device characterization on 4H-SiC & GaN substrates.

• Solid understanding of wide-bandgap semiconductor materials and the strong physics of MOSFET devices

• Ability to teach and transfer knowledge to junior staff members

• Ability to effectively communicate and plan with customers regarding their needs, issues, and demands

ROLE:
IME is leading the effort to establish the industry leading Silicon Carbide R&D program. This program aims to advance 200mm Silicon Carbide technologies in various areas, such as epitaxy, device design, process integration & fabrication, and power module packaging. The main objective is to drive disruptive innovations in power device research, with a specific focus on >1.2KV power MOSFETs. These innovations are intended to enhance automotive technologies, vehicle electrification, safety measures, sustainable energy grids, and industrial automation. Key aspects to demonstrate for this role include high power device design, novel device concepts, doping design, gate oxidation, and wide-bandgap process simulations. To achieve this, we are seeking individual with extensive industry experience in using Synopsys/Silvaco TCAD simulator, relevant device characterization skills, design simulation development abilities, a willingness to mentor junior staffs, and strong interpersonal skills. The candidate will contribute to the wide-bandgap & Silicon Carbide team by utilizing their device knowledge, guiding team on device characterization, implementing state-of-art Silicon Carbide power MOSFETs (Planar, Trench & Super-Junction), and innovative novel power MOSFETs for future applications.

RESPONSIBILITIES:

• TCAD modeling & simulation, novel high power device design, simulation, and device characterization

• Design and simulate high voltage Silicon Carbide MOSFETs (planar, trench, SJ MOSFET, IGBT) with a blocking voltage of >1.2K using Synopsys/Silvaco simulator

• Design & simulate practical and effective junction terminations

• Provide guidances on device structure, optimizing cell, power/performance analysis, process risk assessment, and recommendations for experimental split and improvement

• Develop and apply fundamental MOS device physics-based TCAD modelling & electric field management to calculate band structure, carrier transport, blocking voltage,
switching properties, and thermal management for vertical power devices in the presence of interface state density, gate oxide defects, and defects in Silicon Carbide

• Model transport and carrier scattering in devices operating in extreme ambient conditions

• Collaborate with diverse teams, including process integration, characterization, and circuit design engineers, to analyze and troubleshoot device-related issues during
development

• Serve as a resource for colleagues with less experience, and lead small projects with manageable risks and resource requirements

• Work closely with both internal and external customers to understand customer issues and align their demands. And grow this wide-bandgap team to ~5 headcounts in the
next 3 years.

JOB REQUIREMENTS:

• PhD in Electrical Engineering or related field

• >10 years industrial experience for high power device design and modeling

• Deep knowledge of high voltage, high power MOSFETs (including Planar, Trench, S-J MOSFETs, and IGBTs) design and device characterization on 4H-SiC & GaN substrates.

• Solid understanding of wide-bandgap semiconductor materials and the strong physics of MOSFET devices

• Ability to teach and transfer knowledge to junior staff members

• Ability to effectively communicate and plan with customers regarding their needs, issues, and demands

The Government Technology Agency (GovTech) is the lead agency driving Singapore’s Smart Nation initiatives and public sector digital transformation. As the Centre of Excellence for Infocomm Technology and Smart Systems (ICT & SS), GovTech develops the Singapore Government’s capabilities in Data Science & Artificial Intelligence, Application Development, Smart City Technology, Digital Infrastructure, and Cybersecurity.

At GovTech, we offer you a purposeful career to make lives better. We empower our people to master their craft through continuous and robust learning and development opportunities all year round. Our GovTechies embody our Agile, Bold and Collaborative values to deliver impactful solutions.

GovTech aims to transform the delivery of Government digital services by taking an "outside-in" view, putting citizens and businesses at the heart of everything we do.

Play a part in Singapore’s vision to build a Smart Nation and embark on your meaningful journey to build tech for public good. Join us to advance our mission and shape your future with us today!

Learn more about GovTech at tech.gov.sg.

Digital Design & Development (DCube) is a team in GovTech that seeks to design and develop software applications that help government agencies to better serve the needs of the people of Singapore. To that end, we employ an agile approach towards development, and work towards adopting the best practices and tools used in the top technology companies and organizations.

We are now looking for a top-notch Salesforce developer to join us in this mission, designing world class Salesforce applications for Service Cloud. You will be responsible to gather project requirements, analyse project objective/goal in order to create customer workflows and troubleshoot errors, eventually to create dynamic and scalable Salesforce applications that meet the changing needs of the project.

[What you will be working on]

Work within an agile development team to deliver high-quality software applications according to requirements. This may include:

• Collaborating with stakeholders to validate business requirements,
• Developing Apex classes & triggers to support business needs and custom user interface development
• Using Salesforce APIs to integrate with 3rd party systems and integrate with WoG components/services
• Adhering to Salesforce best practices with proper documentation.

[What we are looking for]

Development/Customization Experience

• Apex development
• Visualforce page development.
• Lighting components development.
• Experience in 3rd party API integrations.
• Experience with data migration through other CRM eg. data loader.

Configuration Experience

• Hands-on configuration experience in administration setup, eg., managing org, users, profiles, roles, security controls, data & support processes configuration.
• Experience in designing custom objects, custom fields, picklists, page layout, workflow, approval processes, validation rules & flow.
• Experience in report & dashboard configuration.
• Experience with OmniStudio & Omniscript will be a bonus.

• Able to work independently
• Good problem solving skills and able to provide optimal solutions.
• Ability to communicate effectively with customers/business stakeholders and provide consultation on Salesforce solutions.
• Certified Salesforce Platform Developer
• Minimum of 5 years of Salesforce development experience, especially with Service Cloud.

GovTech is an equal opportunity employer committed to fostering an inclusive workplace that values diverse voices and perspectives, as we believe that diversity is the foundation to innovation.

Our employee benefits are based on a total rewards approach, offering a holistic and market-competitive suite of perks. These include leave benefits to meet your work-life needs and employee wellness programmes.

We champion flexible work arrangements (subject to your job role) and trust that you will manage your own time to deliver your best, wherever you are, and whatever works best for you.

Learn more about life inside GovTech at go.gov.sg/GovTechCareers.

Stay connected with us on social media at go.gov.sg/ConnectWithGovTech.

Roles and Responsibilities:

• TCAD modeling, simulation, and innovative design of high power electronics devices, as well as device characterization.
• Develop and simulate high power SiC MOSFETs (planar, trench, Super-Junction MOSFET, IGBT) with a blocking voltage exceeding 1.2K using the industry-standard Synopsys/Silvaco simulator.
• Create and simulate practical & efficient junction terminations.
• Model transport and carrier scattering in devices operating under extreme ambient conditions.
• Serve as a valuable resource for colleagues with lesser TCAD power electronics experience and take lead in group projects with managing risks & resource requirements.
• Foster close collaborations with both internal and external customers to fully understand customer issues and requirements.

Job Requirements:

• PhD Degree in Electrical Engineering or related field.
• >2-3 years industrial experience for high power devices design and modeling.
• Thorough understanding of different types of high-voltage, high-power MOSFETs including Planar, Trench, Super-Junction MOSFETs, and IGBTs, with a focus on design and device characterizations.
• Hands-on skill in designing MOSFET/diode layouts.
• Excellent communication skills to effectively engage with customers, address their needs, resolve issues, and meet demands.

Roles and Responsibilities:

• TCAD modeling, simulation, and innovative design of high power electronics devices, as well as device characterization.
• Develop and simulate high power SiC MOSFETs (planar, trench, Super-Junction MOSFET, IGBT) with a blocking voltage exceeding 1.2K using the industry-standard Synopsys/Silvaco simulator.
• Create and simulate practical & efficient junction terminations.
• Model transport and carrier scattering in devices operating under extreme ambient conditions.
• Serve as a valuable resource for colleagues with lesser TCAD power electronics experience and take lead in group projects with managing risks & resource requirements.
• Foster close collaborations with both internal and external customers to fully understand customer issues and requirements.

Job Requirements:

• PhD Degree in Electrical Engineering or related field.
• >2-3 years industrial experience for high power devices design and modeling.
• Thorough understanding of different types of high-voltage, high-power MOSFETs including Planar, Trench, Super-Junction MOSFETs, and IGBTs, with a focus on design and device characterizations.
• Hands-on skill in designing MOSFET/diode layouts.
• Excellent communication skills to effectively engage with customers, address their needs, resolve issues, and meet demands.

Purpose

Responsible for sustainability, profitability and to achieve budget incremental volume plan and placements set for respective key accounts. Efficient utilization and deployment of resources and assets in securing these objectives.

Key Duties / Responsibilities

A: Achieving Sales, Incremental Volume and Profitability

1. Plan and implement overall incremental sales volume, profitability and budget plans. Responsible for growing volume, placement and revenue in key channels and accounts.
2. Identify key accounts for increased business partnerships and growth opportunities via strategic and beneficial to drive sales programme.
3. Manage contract renewals; formulate tenders’ proposals for key accounts. Fulfill existing terms and conditions. E.g. DME/Accruals/Incentives.
4. Conduct regular business reviews internally and with designated key accounts. Re-negotiate terms and benefits to improve profitability, sustainability and resources maximization.
5. Develop business plans, strategies and promotional activities with key accounts to drive volume and revenue indicators.
6. Formulate plans to continuously grow unconventional channels key accounts and convert accounts to increase horizontal and vertical volume growth.
7. Ensure key customers equipment orders are prepared and execute timely and within budget so that equipment procurement targets are supported. Prepare placement plan and forecast for refurbishment action and stock control.
8. Identify new strategic locations for market penetration and expansion opportunities.
9. Plan equipment movement to optimize assets contribution and maximization. Track sales, profitability and net sales revenue of all equipment placed in key outlets with the objectives to improve return on investment as per Company standards.
10. Work closely with all relevant internal and external stakeholders to achieve business objectives.
11. Develop and maintain good customer service and mutually benefiting relationships with existing key clients.
12. Collect data and provide feedback on market intelligence and general industry trends. Identify business strengths, weakness, opportunities and threats to pre-empt and counter-propose business strategies and tactics in the market.
13. Monitor and manage the collection of outstanding payments.

B. Sales and Channel Development

1. Plan and implement promotional and engagement activities and channel activation programs to increase awareness; create brand and market value; optimizing sales volume and revenue.
2. Develop annual major customer plans to include exclusive promotions/sponsorship, total package service and maintenance programs to increase sales volume and pricing.
3. Accountable for meeting and growing set overall channel placement targets and against universe opportunities, net sales revenue, incremental volume and return on investments target.
4. Manage the allocated DME and sponsorships to ensure funds are use appropriately and within budget as per Business Plan.

C. Task Analysis

1. Execute, review and report on progress of sales and recommend relevant action plans accordingly.
2. Submit progress reports and updates on channel development, projects and activities.
3. Monitor potential loss sales volume of equipment and arrest problems.
4. Liaise with Customer Contact Centre, Operations and Technical personnel to ensure smooth follow-up and response to service calls.
5. Liaise with Customer Accounting, Financial Accounting and Commercial Finance on billing, payment, accruals, and settlement matters.

Related Position Requirements/Qualifications

a) Driving License - Class 3

b) University Degree/Diploma with qualifications in Business, Sales and Marketing

c) 3 years’ experience or more in the sales of fast moving consumer products and/or night entertainment industry

d) Preferably with key account servicing/customer service/operations sales and support background

At Cheil, we are passionate about ideas that move.

We believe that the right idea will move seamlessly across channels: from online to offline, above the line to below the line, in-store to out-of-home. It will move brands, move products and most importantly, move people. The right idea will move everything forward.

Established in 1973 with headquarters in Seoul, South Korea, Cheil Worldwide is one of the world’s leading integrated marketing communications networks, with more than 7,200 employees globally in more than 54 offices in 46 countries.

For more information, visit us at: www.cheil.com.

We are inviting candidates for the position of:

Content Publishing / Graphic Design Intern (Full-time internship)

Job description

Working with the Samsung Electronics SEA & Oceania business, you will have the privilege of working within a big data environment where strategic decisions are made, guiding best in class upholding brand compliance.

• Content Audit & Analysis: Work closely with the Content Team to conduct content audits on Samsung.com to ensure content is brand compliant and aligns with our strategic objectives.

• Progress Tracking & Reporting: Analyse, track, and report progress on weekly and monthly reports for multi-market operations, providing insights and recommendations for optimization.

• Training Document Management: Prepare and maintain training documents, Standard Operating Procedures (SOPs), and any other necessary documents to support team operations and knowledge transfer.

• Assist in Design Projects: Execute simple design tasks such as key visual adaptations for regional campaigns, ensuring alignment with brand guidelines and creative direction.

• Asset Management: Organize and maintain digital assets, including images, graphics, and other design elements, to facilitate efficient workflow and collaboration within the team.

Desired Skills and Experience

• Good skill in Excel and PPT

• Good skill in Adobe Illustrator and Photoshop

• Pursuing or recently completed a degree in Graphic Design, Visual Communication, or a related field.

• Analytical and quantitative, with strong attention to detail

• Self-starter with excellent communication and collaboration skills, with the ability to work effectively in a team environment.

• Ability to thrive in a fast-paced, ambiguous, interruptive environment

• Ability to work independently as well as work collaboratively toward a common goal

EDP Renewables APAC is the main subsidiary of EDP Group, a global leader in the renewable energy sector and one of the world’s largest wind producers. With its headquarters in Singapore, EDP Renewables is the leading sustainable development hub for the Asia Pacific region with activities across nine different markets. Our activities are focused on the design, development, management, and operation of renewable energy sources, namely solar, wind, as well as new technologies such as storage.

EDP is a global energy group leading the Energy Transition, Innovation and Sustainability. Using the technology of the future, we create solutions highly focused on the needs of our people and our customers, never neglecting our role and contributions to society. To achieve our goals, we aim to attract diverse people with high potential through the professional opportunities we create.

Join us to be part of a renewable energy leader that reinvests in society through sustainable projects and social as well as cultural causes. You will have the opportunity to actively participate in our global transformation, by changing tomorrow now.

The Senior Design Engineer is responsible for engineering and design of grid connected solar photovoltaic systems (including utility-scale and distributed generation projects). He/she will review solar system engineering designs, modelling, and performance data, and provide engineering support during the development and construction process.

Responsibilities:

• Conduct engineering site audits to collect structural, electrical and related site information for use in the design of commercial and utility-scale solar power systems
• Design and coordinate design of photovoltaic (PV) systems, including system components to suit site condition and in accordance to solar engineering standards (IEC, Singapore Standards etc)
• Design and develop electrical single-line diagram, panel schedules and connection diagram for solar electric systems using computer-aided design (CAD) software
• Prepare and follow up the Master Document Register (MDR)
• Perform solar energy production analysis from designed PV systems and seek to optimize efficiency through cost-benefits analysis
• Review specifications and recommend engineering or manufacturing changes to achieve solar design objectives.
• Evaluate plans or specifications to determine technological or environmental implications.
• Recommend technical design or process changes to improve efficiency, quality, or performance.
• Provide technical direction or support to Project Manager and Engineer during installation, start-up, testing, system commissioning, or performance monitoring.
• Create checklists for review or inspection of completed solar installation projects.
• Analyze costs and benefits of proposed designs or projects and performing cost reduction analyses for solar systems.
• Review of EPC’s Scope of Work, Specifications and comments on design and installation

Requirements:

• At least 3 years of commercial PV system design and engineering
• Bachelor's in Engineering (Mechanical, Electrical or related discipline preferred)
• Experience with low, medium and high voltage power electronics
• Competence in energy modelling software such as PVsyst is mandatory
• Competence in Autocad is mandatory
• Well versed in Microsoft Office, especially Excel
• Must be willing to learn and apply new technologies
• Knowledge of codes such as the IEC, Singapore Standards and construction practices
• Working knowledge of standard electrical calculations, basic structural & mechanical calculation

When you join EDP Renewables APAC, you will have access to:

• Professional experience in a leading global company in the renewables industry with flexible work conditions
• Recognition through remuneration compatible with the role and other additional benefits
• Opportunities for personal and professional development, e.g. cross-cutting projects, mobilities and volunteering

About EDP Group:
As a socially responsible company, we incorporate our values and practices with the principles of Diversity and Inclusion. To achieve all our objectives, we intend to attract, develop and retain different profiles, assuming diversity as a key factor and differentiator of fundamental innovation in our organisation. We welcome and value all people, and we are committed to the inclusion and sense of belonging of each person who is part of the EDP Group.

What makes us proud as an employer:
• TOP Employer APAC, Singapore 2024 certification
• TOP Employer Europe 2024 certification
• Bloomberg Gender Equality Index 2021
• Top Workplaces US 2021
• Certification in Conciliation (Excellence) by the Más Familia Foundation

We are hiring Junior/Senior Interior Designers !

Drop us an email with your resume today!

Email: [email protected]

Responsibilities:

• understand homeowner requirement and propose space planning with layout and material
• draw in 2D CAD & 3D Sketch Up
• responsible to work out quotation
• responsible to supervise work progress and meet the timeline
• responsible to liaise with suppliers and subcontractors in order to have good quality works

Requirements:

• O level(Min), Diploma, Degree/Bachelor
• Min 1 years’ experience in interior design or construction project management or related experience
• Strong problem solving and analytical skills
• Able to converse in English and Mandarin(in order to handle queries and concerns from English and Chinese speaking counterparts in regards with the interior design related matters.)
• Creative, independent, self-discipline, willing to learn, love to talk to customer and meticulous
• Good communication and like to do presentation, able to meet client at weekend and public holidays

Why join us?

• SIDA Best Design Award Winner
• Singapore Good Design Award Winner
• Qanvast Top 3 Interior Design Firm
• SuperTrust Award Winner Interior Design Firm
• Well-Known Boutique Interior Design Firm
• New 3500sf Design Show Room
• Plenty of opportunities to grow as a pioneer in our company
• Salary based or Profit sharing based

Roles & Responsibility

-Content Creations for Social Media (Instagram, Facebook, Youtube, Website etc)

-Plan out social media content (graphics, videos, photography)

-Craft Marketing and Social Media campaigns and strategies

-Promote content on social networks and monitor engagement (e.g. comments and shares)

-Brainstorm ideas and creative ideas for daily content in the form of mainly images, but also video and articles

-Execution of content creation: shooting videos, photography etc.

-Other ad-hoc duties as assigned by the company

Requirement

-At least 1 year of experience in related field

-Preferably entry-level specialized in Graphic Design/ Photograghy/ Film Production/ Film, Sound and Video.

-Preferably skilled and experienced in handling operating camera

-Creative, independent, self-discipline and willing to learn

Job Description

• Working on 6nm and below advanced process project APR and Timing/PI sign-off
• Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros)
• Take the Block or Block coordinator role for complex blocks
• Do early prediction for critical APR/Timing/PI issues

Job Requirements

• APR/Timing/PI hands-on/tapeout experience on complicated hierarchical chip
• TCL/Perl/Python/C/C++ programming skill
• Have advanced process(n6 or below) experience is a plus
• Excellent communication and team work spirit

Job Description

• Working on 6nm and below advanced process project APR and Timing/PI sign-off
• Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros)
• Take the Block or Block coordinator role for complex blocks
• Do early prediction for critical APR/Timing/PI issues

Job Requirements

• APR/Timing/PI hands-on/tapeout experience on complicated hierarchical chip
• TCL/Perl/Python/C/C++ programming skill
• Have advanced process(n6 or below) experience is a plus
• Excellent communication and team work spirit

• We are a chip design service company invested by an international consortium and founded by a senior chip design technical team.
• The company is headquartered in Singapore and will take root in Singapore for long-term development.
• In the future, we will also open branches in China, Japan and other places. The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.
• We have rich industry experience and deep practical accumulation in ASIC design and business management.

Our office is located in one North and walking distance from MRT.

We Provide competitive salary and compensation package for the right candidate.

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered. ( for excellect junior candidates with 3+ years experience will be considerated )

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

Job description:

• Design Engineer for embedded memory design and verification in advanced nodes for high performance ASIC targeting Cloud AI/ Data Center Network Switch and 5G infrastructure, CPU and AP-SOC
• Collaborate closely with product and architecture teams to define, design and develop high performance customized semiconductor memories to meet PPA specifications and integration.
• Innovate, design, and incorporate special circuits and methodology to achieve best-in-class PPA for custom and compiler memories.
• Develop timing/power/noise characterization flow for advanced node memory compiler. Strong focus on design automation for SRAM compiler, big data analysis and design verification
• Develop memory analysis flow for PPA check

Job requirements:

• 3+ years of hands on experience in design of embedded memories (SRAM, TCAM) for high performance processors or ASICs in advanced nodes (3nm/5nm)
• Good understanding of Digital Circuit design techniques in FinFet technologies.
• Exposure to complete design cycle of SRAM memory and compiler development
• Supervise layout engineers and review layout for optimality.
• Experience in using industry standard schematic entry tools, advanced transistor level simulators (XA, HSIM, FINESIM)
• Experience with LEC tools (ESPCV)
• Knowledge of RTL and place and route tools is a plus
• Ability to come up with design verification and test plans
• Silicon debug and bring up experience is a plus
• Working knowledge of scripting in Perl/Python
• Willingness to collaborate closely with cross functional teams across the globe