Job Description:
● Perform analog/mixed signal layout for short range RF wireless applications (i.e WiFi, BT etc) using advanced sub-micron CMOS/SiGe/GaAs technologies
● Configure foundry DRC/LVS rules and perform physical verifications on completed RFIC layout such as DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.
● Run layout parasitic extraction in preparation for post layout simulation and optimization.
● Integration of RFIC chip for tape out to foundry.
Skills / Qualifications:
● More than 3 years RFIC layout and Top level IC integration experience in CMOS (28nm, 16nm, 7nm, 5nm) /SiGe/GaAs process
● Experience in layout of RF building blocks such as PA / LNA / Mixer / VCO / IF filter / Balun / Inductor etc
● Must have strong knowledge in RFIC layout verification flow (i.e DRC, ERC, LVS, ANT etc) and usage of CAD layout verification tools such as Cadence, Mentor Graphics tools
● Highly motivated, able to work independently and demonstrates strong troubleshooting and communication skills
● Some experience in script writing such as pearl, skill etc will be advantageous
● Good interpersonal and creative skills with the ability to multitask in a demanding and fast paced environment.
● Good team player
● Minimum Bachelor Degree in Electrical Engineering or any relevant courses.
Interested candidate who wish to apply for this position, please click on APPLY NOW
EA License No.: 01C4394 | PERSOLKELLY Singapore Pte Ltd
EA Registration No.: R23117518 | Heah Sian Wei
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