Position Overview:
The Senior/Staff Design Engineer will be responsible for developing micro-architecture for ISP and CV related algorithms, utilizing RTL design using Verilog/System Verilog coding and HLS tools like Catapult. They will analyze metrics such as power, performance, and area to meet key objectives, collaborate with architects and DV Engineersfor efficient verification signoff, and support FPGA tasks such as emulation,validation, and debugging.
Responsibilities:
- Develop micro-architecture for ISP and CV algorithms.
- Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
- Analyze and optimize metrics like power, performance, and area.
- Cooperate with verification architects and DV engineers to ensure high quality IP delivery.
- Support backend team for SoC signoff.
- Oversee FPGA tasks including emulation, validation, and debugging.
Qualification/Requirements:
- Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
- Experience: Minimum 5yearsand aboveof experience in ASIC design. Expertise in image signal processing projects is beneficial.
- Technical Skills:
- - Advanced proficiency in HDL languages (Verilog, System Verilog).
- - In-depth knowledge of all phases of ASIC frontend design and sign-off.
- - Extensive experience in image/vision/video data processing or algorithm acceleration.
- - Proficiency in scripting languages like Python, Perl, or C/C++.
- Soft Skills: Excellent leadership, teamwork, and communication skills.
- Additional Notes:Stronganalytical skills and the ability to lead complex projects independently and within teams.
