As a senior chip interconnect design expert, you will be responsible for driving the technological development of AI SoC interconnect systems, defining innovative and efficient interconnect solutions. Main responsibilities include but are not limited to:
Defining, developing, and optimizing high-performance PCIe Gen 5/6, CXL 2.0/3.0, and advanced Chip-to-Chip and Die-to-Die interconnect architectures to meet the performance and scalability requirements of AI SoCs.
- Defining system architecture, hardware architecture design, and innovations related to advanced interconnect technologies.
- Designing and innovating system architectures related to new computing architectures (e.g., near-memory computing) and memory technologies (memory pooling, NVM).
- Designing SoC interconnect hardware architecture, implementing hardware code, and simulation, including interface handling, interconnect protocol design, and in-line computation acceleration.
- SI/PI debugging, hardware platform setup, debugging, and testing.
- Developing and maintaining drivers and system software, and performing debugging.
Requirements:
- Master’s degree or higher in Integrated Circuits, Electronic Engineering, Computer Science, or related fields.
- At least 5 years of experience in SoC design and architecture.
- Familiar with high-speed interconnect protocols (C2C, D2D) with at least 2 years of experience in chip high-speed interconnect design and development.
- Familiar with Serdes required for various protocols, with Serdes IP debugging experience.
- Proficient in hardware programming (Verilog) or software programming (C++, Python), with strong coding abilities preferred.
- Familiar with the Linux kernel and hardware drivers, with extensive driver development experience preferred.
- Strong problem-solving abilities, capable of independently performing system-level analysis and design.
- Strong team collaboration spirit, excellent communication skills, and project management abilities.
- Proficiency in RISC-V architecture or NOC architecture is preferred.
DISCLAIMER
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.
Enna Chong
EA 12C6130/ R22109962
