Company Overview
The team has more than 15 years of experience developing 1G/2.5G/5GBase-T Ethernet physical layer PHY and switch chips for data centers, enterprise networks, and gateways and has successfully developed multiple generations of the most competitive products.
The company is headquarted in Kunshan, and the R&D team is located in Kunshan, Suzhou, Shanghai, and Singapore and plans to setup an R&D center in Silicon Valley.
The company is currently developing Ethernet PHY, gateway, and TSN switching chips. The target market is automotive & unpiloted driving, China's intelligent manufacturing, rail transit, and intelligent grid building industry provide domestic chips with "Independent intellectual property rights, independent and controllable.
We offer attractive salary commensurate with work experience + AWS + Bonus + Stock options
Job Responsibilities:
- Help define analog system design specifications and architectures.
- Lead analog designs during product development.
- Participate in the design and realization of high-speed low-power small-area network chips.
- Responsible for the design and verification of analog and mixed-signal circuits, particularly the CMOS signal processing circuits with profession in one of these areas, RX(e.g., AFE, ADC), TX(Serializer, DAC), PLL, LDO, ESD/EMC suppression etc.
- Support high-level functional development and verification of analog and mix-circuit circuitry.
- Cooperate with product definition, layout implementation, lab test and verifications.
Job Requirements:
- Master with > 7 years' experience or PhD with > 4 years' experience in high-performance analog/mixed-signal ICs.
- Proven experience in IC design including chip tape-out and lab evaluation of design.
- Solid experience in using EDA CAD tools and performing Analog Custom Layout.
- Experience in measuring IC performance and debug of design to correlate simulations to measurements.
- Deep understanding of fundamental, including: detailed transistor level design, device physics, control/feedback loop stability analysis.
- Direct project experience in at least one of the following areas a plus: ADC-DAC design PLL or clock/freq generation design.
- Knowledge & experience in Verilog coding a plus.
- Strong communication skills and good team player.
