Total 16 staff nurse job vacancies in Engineering category in D19 Serangoon Garden, Hougang, Sengkang, Punggol

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

About DKatalis

DKatalis is a financial technology company with multiple offices in the APAC region. In our quest to build a better financial world, one of our key goals is to create an ecosystem-linked financial services business.

DKatalis is built and backed by experienced and successful entrepreneurs, bankers, and investors in Singapore and Indonesia who have more than 30 years of financial domain experience and are from top-tier schools like Stanford, Cambridge London Business School, JNU with more than 30 years of building financial services/banking experience from Bank BTPN, Danamon, Citibank, McKinsey & Co, Northstar, Farallon Capital, and HSBC.

About the role

You will be part of a cross-functional agile engineering team (squad) responsible to build, deploy and run (support) one or more of our digital products, focusing on full-stack experience to build robust & resilient systems (front-end & back-end).

You will work closely with Engineers, Product, Design, and other stakeholders, collaboratively ensuring quality gets built in the product, get to see your impact in everyday lives of many people, and have great fun while doing it.

You will share your learnings within and beyond your team (squad) and mentor budding engineers for good engineering practices

What will you do

• Working with engineering+product owners to design, refine and develop the product, from concept to implementation.
• Main contributor in creating best in-class product & experience for our customers by designing, building, scaling, and evolving our platforms, services, and tools
• Communicate, collaborate and work effectively across cross functional teams in a multicultural environment
• Mentor a team of highly talented and motivated engineers
• Ensure the performance, security, and responsiveness of applications built
• Continuously improve code quality, product execution, automatization and customer delight

What you need to have

• You have at least 10+ years of professional experience in a similar role developing highly scalable applications
• Good written and spoken English
• Hands on expertise in Java / Javascript or its derivatives (Typescript, NodeJS, Scala, Kotlin, Springboot, etc)
• Have hands on experience on one of this front-end development (Flutter Preferred)
• Experience to Lean/XP practices (TDD, Pair Programming, Continuous Integration/Delivery for both Mobile & Back-end)
• Experience working in Agile Software development
• Communicate, collaborate, and work effectively across distributed teams in a multicultural environment.
• You’re excited about delivering end-to-end experiences and care about your software architecture across the front-end, back-end, and the APIs that glue them together
• A passion for quality and best practices but with a pragmatism that understands the
  balance between perfection and delivering value in a timely manner.
• Enjoys mentoring more junior engineers on good engineering practices & share knowledge

What you do

Be part of the team that validates the physical sign-off of our chips, powering the brands we love every year with 2 billion consumer electronic products such as digital TVs, home audio devices, DVD/Blue-ray players, smartphones, tablets, networking and connectivity products, and many more. As a member of the MediaTek Physical Verification Sign-off team, you will be responsible for ensuring the manufacturability and reliability of IC designs through rigorous physical verification processes to enable the success of our chips tape-out. Join us in shaping the future of technology and making a real impact on the world!

• Responsible for assembling of various design system into a full chip.
• Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.
• Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and schematic of the IC design.
• Execute electrical rule check (ERC) to identify potential electrical issues and ensure the integrity of the design.
• Perform antenna and electrostatic discharge (ESD) checks to prevent potential reliability, latch-up, leakage issues.
• Collaborate with design and layout teams to address and resolve physical design issues and optimize the layout for manufacturability and reliability.
• Contribute to the development and improvement of physical verification methodologies and flows.
• Work closely with process technology teams to understand and address process-related challenges and constraints.
• Participate in tape-out activities and ensure that the physical design meets the required quality and reliability standards for fabrication.

What you bring

• With minimum 8 years of relevant experience.tronic Engineering / Computer Science or equivalent..
• With minimum 8 years of relevant experience
• Solid understanding of physical design concepts, IC manufacturing processes, and semiconductor device physics.
• Proficiency in using physical verification tools such as Calibre, IC Validator, or other industry-standard DRC/LVS tools.
• Experience with scripting languages such as TCL, Perl, or Python for automation and tool customization.
• Strong problem-solving skills and the ability to analyze and debug complex physical design issues.
• Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
• Familiarity with EDA (Electronic Design Automation) tools and design methodologies is a plus.
• Proficient in UNIX (Linux) platforms.
• Strong communication skills, problem solving and analytical skills.

Location: One North, Singapore

Who We Are

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.
  

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. 2 years of relevant experience in similar field.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

Job Description

Meet the Team

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

As Senior Staff Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips.

Responsibilities

• Block and IP Verification
• Block-level verification to validate block performance and adherence to requirements
• Generate and execute verification plan based on specifications
• Architect and implement test benches using UVM-based constrained-random and formal methods
• Coverage definition, implementation, and analysis
• Formal Verification of mixed-signal IP integration, including real-number modeling
• SoC Integration and Verification
• Define, test and debug use cases for the SoC
• Verify and debug low-power design
• Flows and Methodology
• Improve flows and methodologies to streamline IP development and integration.

Skills You Will Need
Minimum Qualifications:

• Min. 15 years of IC design experience for senior positions. Open to junior candidates with strong foundation.
• Industry experience developing test benches and verification components with SystemVerilog and UVM is required
• Knowledge of scripting/language (Python, PERL, shell, TCL)
• Design/Verification skills such as Software/Firmware coding (C), SystemVerilog Assertion and coverage analysis, Low-power implementation (UPF), Mixed Signal Real Number Modeling (RNM, Spice)

Benefits & Perks:
You can look forward to the following benefits:

• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• Located above Tai Seng MRT
• Flexible work policy

Company Overview: Halo Microelectronics, a developer of Analog and Mixed Signal Integrated Circuits enabling energy-efficient smart systems, is seeking experienced Digital Design Engineers to join the Singapore design team.

Job Responsibilities:

1) Participate in formulating digital circuit design specifications.

2) Perform Verilog RTL to implement modular digital circuits.

3) Conduct RTL, Pre, and Post simulation verification.

4) Use PR tools for digital layout generation.

5) Responsible for front-end implementation, including DC PT Formality DFT (measurable) design, low power consumption design, etc.

6) Work with Analog designers to conduct chip verifications.

7) Work with test engineer to develop test plans and assist in debugging.

Qualifications:

1) Strong educational or industrial background in digital circuit design.

2) Experience with digital IC design and understand the whole flow of IC design flows.

3) Demonstrate good communication and interpersonal skills.

4) Must be able to perform as a team member and able to work independently.

Requirements:

1) Master’s degree or above, major in electronics or microelectronics.

2) 2 years above working experience for digital or mix signal design.

3) Familiar with digital circuit design tools.

4) Good knowledge of analog or mixed signa circuit design.

5) Extensive experience in circuit hybrid simulation tools.

6) Good communication and interpersonal skills.

About DKatalis

DKatalis is a financial technology company with multiple offices in the APAC region. In our quest to build a better financial world, one of our key goals is to create an ecosystem-linked financial services business.

DKatalis is built and backed by experienced and successful entrepreneurs, bankers, and investors in Singapore and Indonesia who have more than 30 years of financial domain experience and are from top-tier schools like Stanford, Cambridge London Business School, JNU with more than 30 years of building financial services/banking experience from Bank BTPN, Danamon, Citibank, McKinsey & Co, Northstar, Farallon Capital, and HSBC.

About the role

You will be part of a cross-functional agile engineering team (squad) responsible to build, deploy and run (support) one or more of our digital products, focusing on full-stack experience to build robust & resilient systems (front-end & back-end).

You will work closely with Engineers, Product, Design, and other stakeholders, collaboratively ensuring quality gets built in the product, get to see your impact in everyday lives of many people, and have great fun while doing it.

You will share your learnings within and beyond your team (squad) and mentor budding engineers for good engineering practices

What will you do

• Working with engineering+product owners to design, refine and develop the product, from concept to implementation.
• Main contributor in creating best in-class product & experience for our customers by designing, building, scaling, and evolving our platforms, services, and tools
• Communicate, collaborate and work effectively across cross functional teams in a multicultural environment
• Mentor a team of highly talented and motivated engineers
• Ensure the performance, security, and responsiveness of applications built
• Continuously improve code quality, product execution, automatization and customer delight

What you need to have

• You have at least 10+ years of professional experience in a similar role developing highly scalable applications
• Good written and spoken English
• Hands on expertise in Java / Javascript or its derivatives (Typescript, NodeJS, Scala, Kotlin, Springboot, etc)
• Have hands on experience on one of this front-end development (Flutter Preferred)
• Experience to Lean/XP practices (TDD, Pair Programming, Continuous Integration/Delivery for both Mobile & Back-end)
• Experience working in Agile Software development
• Communicate, collaborate, and work effectively across distributed teams in a multicultural environment.
• You’re excited about delivering end-to-end experiences and care about your software architecture across the front-end, back-end, and the APIs that glue them together
• A passion for quality and best practices but with a pragmatism that understands the
  balance between perfection and delivering value in a timely manner.
• Enjoys mentoring more junior engineers on good engineering practices & share knowledge

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. of 8 years of relevant verification experiences.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

Overview

We are looking for result-driven candidates who would thrive under a fast-pace working environment and having a strong desire to make an impact in their organization.

What you will do

• Own the entire layout implementation process: schedule estimation, floorplanning, layout construction, physical verification and memory compiler leaf-cell creation
• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely with multi-functional members to optimize layout realization according to the desired power, performance and area optimization requirement
• Candidates with strong soft skills could be tasked to undertake project management, coaching of new hires/interns or workflow improvement initiative

What you bring

• Bachelor’s degree in Electrical/Electronic/Computer Engineering or equivalent
• At least 8~10 years of direct experience in custom Memory layout implementation (SRAM/ROM/TCAM/CIM) in advanced finFET/GAA process nodes
• Proficient in understanding DRM of advanced CMOS technologies and have a good understanding of deep sub-micron and DFM issues (eg. WPE, LOD effects, etc.)
• Strong knowledge in floor-planningtechniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integrationflow
• Strong knowledge in executing and debugging various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc
• Proficient in Synopsys/Cadence layout editors
• Ability in script programming (eg. Python, Tcl, Perl or C-shell) is a plus
• Team player and effective in cross-team communication and time management

Location: One North, Singapore

Why MediaTek

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

The Job

• Develop timing/power/noise characterization flow for advanced node memory compiler.
• Strong focus on design automation for SRAM compiler, big data analysis and design verification.
• Develop memory analysis flow for PPA check.

The Talent

• Bachelor's Degree (with min. 6 years of relevant industry experience) /Masters Degree (with min. 4 years of relevant industry experience)/ PhD in Electrical and Electronic Engineering/Computer Engineering/Computer Science.
• Knowledge of SRAM/ROM memory functionality and high speed, low power memory design architecture.
• Experience in spice simulation and understand CMOS layout view, Verilog coding is preferable.
• Proficient in script programming with Perl or Python3.

What you will do

• Responsible for Standard Cell Library Characterization for leading edge process node (7nm/5nm/4nm/3nm), as the pioneer to setup design platform for Mediatek projects.
• Perform timing/power/constraint/noise/variation modeling, analysis and flow development for >15K logic circuit for one process node.
• Testchip design and Si data analysis flow development for advanced technology node (<7nm), including big data processing and visualization.

What you bring

• BS/MS in Engineering/Computer Engineering/Computer Science.
• Basic knowledge of IC design and circuit design.
• Basic knowledge of UNIX/LINUX environment and any programming language, e.g. Python, Perl, Tcl, C/C++.
• Familiar with foundation IP (Std-cell, Memory, I/O) design and/or CAD is a plus.
• Knowledge of spice simulation, data analysis, machine learning is a plus.

Location: One North, Singapore

Digital IC Verification

• Develop and maintain verification environment for IP modules and SOC level using UVM methodology.
• Write, review and implement verification plan.
• Create and debug test cases.
• Perform code coverage analysis on IP modules and SOC level.
• Continuous improvement of the verification flow.

Additional responsibilities:

a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.

b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Knowledge and skill requirements:

• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in digital IC verification. Staff level will be considered for engineer with more years of experiences.
• Working experiences from design to tape-out are essential
• Experience in system Verilog and UVM verification methodology
• Experience in using EDA tools from Synopsys or Cadence
• Knowledge and working experience in one or more of the following is a plus:

1. Digital and mixed-signal design
2. Microcontroller and graphics processor products
3. Knowledge in connectivity technology such as USB, UART, SPI, I2C, AHB.
4. Embedded programming using C language.

Working Conditions:

- Working conditions are normal for an office environment.

- Work requires willingness to work a flexible schedule.

Job Responsibilities:-

• Perform verification of modules and subsystems including digital signal processing modules, networking components (eg. packet processing/protocol accelerator modules) as well as in high speed peripheral interfaces (integration of analogue IP modules such as SerDes PHYs) for complex IC/SOCs
• Own and create verification plans based on specifications
• Develop testbenches in SpecmanE/SV/UVM environments for RTL simulations and GLS
• Create and run directed and random testcases to achieve coverage targets and validate functional and performance requirements of design
• Support and provide verification expertise and documentation to meet engineering challenges, schedule and quality goals through executing in-house methodology and standard industry tools
• Collaborate closely with cross domain teams including silicon/system architects, designers, system validation and SW engineering teams to ensure successful pre/post silicon validation of these IPs or subsystems in ASIC/SOC products
• Create solutions to support continuous improvement and learning in digital IP verification methodologies and flows

Job Requirements:-

• Bachelor or Master’s Degree in Electronics/Communications Engineering
• 8 years and above of experience in Digital IC verification at IP/subsystem level
• Strong fundamentals and proven expertise in digital IC verification methodology, programming and SOC
• Specialization in High-Speed Interfaces and industry protocols standards such as PCIe, USB, Ethernet IEEE 802.3 standards, AXI, AHB buses etc.
• Strong RTL verification skills using SpecmanE/C/SystemVerilog/UVM methodology
• Expertise in RTL simulations and GLS debug using industry standard tools
• Expertise to achieve comprehensive Functional and Code coverage using industry standard tools
• Knowledge and expertise in understanding standards, specification or requirements documents and define test environment, test plan to meet the requirements
• Experience in development of Verification IP, Bus functional models, Monitor, Protocol checkers and setting up of regression environment
• Knowledge and hands on experience of scripting languages (Python, Perl) and expertise in using them to automate verification tasks and regressions
• Knowledge and hands on experience with testing pre-silicon prototypes as well as post silicon testing in a lab environment is desirable
• Strong analytical, problem solving and debugging skills
• Proven written and verbal communication skills that demonstrate clarity of thought and conviction

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Overview

We are looking for result-driven candidates who would thrive under a fast-pace working environment and having a strong desire to make an impact in their organization.

What you will do

• Own the entire layout implementation process: schedule estimation, floorplanning, layout construction, physical verification and memory compiler leaf-cell creation
• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely with multi-functional members to optimize layout realization according to the desired power, performance and area optimization requirement
• Candidates with strong soft skills could be tasked to undertake project management, coaching of new hires/interns or workflow improvement initiative

What you will bring

• Bachelor’s degree in Electrical/Electronic/Computer Engineering or equivalent
• At least 8~10 years of direct experience in custom Memory layout implementation (SRAM/ROM/TCAM/CIM) in advanced finFET/GAA process nodes
• Proficient in understanding DRM of advanced CMOS technologies and have a good understanding of deep sub-micron and DFM issues (eg. WPE, LOD effects, etc.)
• Strong knowledge in floor-planningtechniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integrationflow
• Strong knowledge in executing and debugging various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.
• Proficient in Synopsys/Cadence layout editors
• Ability in script programming (eg. Python, Tcl, Perl or C-shell) is a plus
• Team player and effective in cross-team communication and time management

Location: One North, Singapore

Why MediaTek

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Job Responsibilities:-

• Perform verification of modules and subsystems including digital signal processing modules, networking components (eg. packet processing/protocol accelerator modules) as well as in high speed peripheral interfaces (integration of analogue IP modules such as SerDes PHYs) for complex IC/SOCs
• Own and create verification plans based on specifications
• Develop testbenches in SpecmanE/SV/UVM environments for RTL simulations and GLS
• Create and run directed and random testcases to achieve coverage targets and validate functional and performance requirements of design
• Support and provide verification expertise and documentation to meet engineering challenges, schedule and quality goals through executing in-house methodology and standard industry tools
• Collaborate closely with cross domain teams including silicon/system architects, designers, system validation and SW engineering teams to ensure successful pre/post silicon validation of these IPs or subsystems in ASIC/SOC products
• Create solutions to support continuous improvement and learning in digital IP verification methodologies and flows

Job Requirements:-

• Bachelor or Master’s Degree in Electronics/Communications Engineering
• 8 years and above of experience in Digital IC verification at IP/subsystem level
• Strong fundamentals and proven expertise in digital IC verification methodology, programming and SOC
• Specialization in High-Speed Interfaces and industry protocols standards such as PCIe, USB, Ethernet IEEE 802.3 standards, AXI, AHB buses etc.
• Strong RTL verification skills using SpecmanE/C/SystemVerilog/UVM methodology
• Expertise in RTL simulations and GLS debug using industry standard tools
• Expertise to achieve comprehensive Functional and Code coverage using industry standard tools
• Knowledge and expertise in understanding standards, specification or requirements documents and define test environment, test plan to meet the requirements
• Experience in development of Verification IP, Bus functional models, Monitor, Protocol checkers and setting up of regression environment
• Knowledge and hands on experience of scripting languages (Python, Perl) and expertise in using them to automate verification tasks and regressions
• Knowledge and hands on experience with testing pre-silicon prototypes as well as post silicon testing in a lab environment is desirable
• Strong analytical, problem solving and debugging skills
• Proven written and verbal communication skills that demonstrate clarity of thought and conviction

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Responsibilities:

• Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS.
• Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP.
• Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

Requirement:

At least 4 years of experience in Physical Design and Signoff

[Skills]

>> Synthesis::

PPA improvement through synthesis recipe exploration for better perf, power, and area.

>> Physical design ::

Floor Planning, Place & Route followed by Timing and Physical Closure

>> Signoff ::

PI : PG mesh spec selection, Bump/RDL planning, IR closure

PV : DRC, LVS, ANT, ERC closure

STA : Block level timing closure