Physical design engineer
Netlist to GDSII at block level, Subsystem Level and at Full chip.
Worked on multiple tapeouts on Netlist to GDSII
Hierarchical partitioning and budgeting of block-level subsystems.
Implementation of high performance (HP) cores, low power designs
Node experience upto 7nm, 10nm, 14nm, 28nm.
Timing Signoff in loop through STA and ECO cyc...