What you will do
[Physical Design]
Work for physical design and development activities of MediaTek’s Ghz ARM-based microprocessors
Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and
Technical disciplines include synthesis, floor-planning, place and route, RC extract...
What you will do
APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO
What you bring
Apr hands on for n5/n4/n3e process using I...
What you will do
Responsible for standard cell test key design of leading-edge process node (4nm/3nm/2nm), from schematic netlist to gds.
Work with layout engineer for test key implementation and physical verification including DRC/LVS/ERC/ANT.
Perform layout extraction, simulation, testing data collection and processing.
Analyze simulatio...
What you will do
[Physical Design]
Work for physical design and development activities of MediaTek’s Ghz ARM-based microprocessors
Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and
Technical disciplines include synthesis, floor-planning, place and route, RC extract...
What you will do
Develop and review test plans.
Develop verification environment/testbench in Module/IP/SOC level.
Develop verification IP and reference model.
Implement test with randomization based coverage driven verification methodology.
Implement functional and functional/code coverage closure.
Hands-on code/debug with UVM, System...
What you will do:
Responsible for the design and verification of digital IC circuit blocks within analog/RF IPs.
Create analog/RF macro models for system level co-simulation verification.
Testing & Debugging of IC prototypes (with system verification engineers).
Support of IC to mass production ready.
Continual support / debug of fi...
Job Description:
Design of RF/Analog/Mixed-signal IC circuit blocks / IPs based on specifications (performance, area, power consumption).
Realize IC layout with floor planning and performance considerations (with layout engineers).
Testing & Debugging of IC prototypes (with system verification engineers).
Support of IC to mass producti...
What you will do
Design and verification of digital IC circuit blocks within analog/RF IPs.
Create analog/RF macro models for system level co-simulation verification.
Testing & Debugging of IC prototypes (with system verification engineers).
Support of IC to mass production ready.
Continual support / debug of field related issues or...
What you will do
APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO
What you bring
Apr hands on for n5/n4/n3e process using I...
What you will do
Develop and review test plans.
Develop verification environment/testbench in Module/IP/SOC level.
Develop verification IP and reference model.
Implement test with randomization based coverage driven verification methodology.
Implement functional and functional/code coverage closure.
Hands-on code/debug with UVM, System...
What you will do
Responsible for standard cell test key design of leading-edge process node (4nm/3nm/2nm), from schematic netlist to gds.
Work with layout engineer for test key implementation and physical verification including DRC/LVS/ERC/ANT.
Perform layout extraction, simulation, testing data collection and processing.
Analyze simulatio...
What you do
Design of RF/Analog/Mixed-signal IC circuit blocks / IPs based on specifications (performance, area, power consumption)
Realize IC layout with floorplanning and performance considerations (with layout engineers)
Testing & Debugging of IC prototypes (with system verification engineers)
Support of IC to mass production ready...
Project Overview
The "Mens, Manus and Machina—How AI Empowers People, Institutions and Cities in Singapore (M3S)" project is driven by the goal of investigating the nature of work, redefining our relationship with technology, and exploring how institutions can adapt to foster livability, sustainability, innovation, and social welfare.
Successful a...