Total 109 Senior Executive design editor job vacancies in D05 Clementi New Town, Hong Leong Garden, Pasir Panjang

Job responsibilities

1. Responsible for Physical Design for Full chip/Blocks covering Floor planning, Placement, Area Optimization, Clock tree synthesis, Placement optimizations, Routing, Timing Closure, power network design, Voltage drop analysis, RC extraction, etc.

2. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other R&D Engineers.

3. Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.

Job requirements

1. Bachelor's degree or above, major in Microelectronics / Electronic engineering / Communication engineering and other related fields.

2. More than 3 years working experience in layout and wiring of 40 nm and below technology.

3. Able to independently complete the whole chip P&R process and IR_ Drop, STA, low power inspection.

4. Familiar with TCL or Perl and other scripting languages.

5. Familiar with design flows and EDA tool software.

6. Familiar with Sign-off methodology and the use of EDA tool software in STA / power.

Job Description: As a Project Executive in Interior Design, you will be responsible for overseeing the planning, coordination, and execution of design projects. You will manage a team of designers, liaise with clients, and ensure that all projects are delivered on time, within budget, and to the highest standards of quality.

Key Responsibilities:

• Lead and manage multiple interior design projects simultaneously, from initial concept to final installation.
• Develop project timelines, budgets, and resource allocations.
• Collaborate with clients to understand their vision and requirements, providing expert guidance throughout the design process.
• Coordinate with architects, contractors, and vendors to ensure design integrity and successful execution.
• Monitor project progress, conduct site visits, and implement corrective actions as necessary.
• Facilitate communication between internal teams and external stakeholders to ensure alignment and transparency.
• Prepare and present project updates and reports to clients and senior management.

Qualifications:

• Diploma or Bachelor’s degree in Interior Design, Architecture, or a related field.
• 3 years of experience in project management within the interior design industry.
• Strong knowledge of design principles, project management methodologies, and industry standards.
• Proficiency in design software (e.g., AutoCAD, SketchUp, Adobe Creative Suite).
• Exceptional leadership, organizational, and communication skills.
• Ability to manage multiple projects and adapt to changing priorities.

What We Offer:

• Opportunities for professional development and advancement.
• A creative and collaborative work environment.

• We are a chip design service company invested by an international consortium and founded by a senior chip design technical team.
• The company is headquartered in Singapore and will take root in Singapore for long-term development.
• The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.
• We have rich industry experience and deep practical accumulation in ASIC design and business management.

Our office is located in one North and walking distance from MRT.

We Provide competitive salary and compensation package for the right candidate. We are work-life balance and friendly to employees with various benefit.

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered. ( for excellect junior candidates with 3+ years experience will be considerated )

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

• Prepare work schedule.
• Prepare P/O or W/O for suppliers and tradesmen.
• Liaise with clients, suppliers and tradesmen for delivery and commencement of work.
• Monitor site progress and inform sales personnel and clients accordingly.
• Ensure quality of work is done according to design provided by sales personnel.
• To co-ordinate touch-up or rectification works, if any.
• To ensure project is completed on time according to work schedule.
• Ensure proper housekeeping on site.

Job Description:

- Perform Civil, Structural Analysis and Design to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- To Lead and Mentor Junior Engineer in Performing Engineering Task

- Reporting to Principal Engineer / Management

Job Requirements:

- Candidate must possess at least a Master's Degree /Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 4 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

Roles and Responsibilities:

• TCAD modeling, simulation, and innovative design of high power electronics devices, as well as device characterization.
• Develop and simulate high power SiC MOSFETs (planar, trench, Super-Junction MOSFET, IGBT) with a blocking voltage exceeding 1.2K using the industry-standard Synopsys/Silvaco simulator.
• Create and simulate practical & efficient junction terminations.
• Model transport and carrier scattering in devices operating under extreme ambient conditions.
• Serve as a valuable resource for colleagues with lesser TCAD power electronics experience and take lead in group projects with managing risks & resource requirements.
• Foster close collaborations with both internal and external customers to fully understand customer issues and requirements.

Job Requirements:

• PhD Degree in Electrical Engineering or related field.
• >2-3 years industrial experience for high power devices design and modeling.
• Thorough understanding of different types of high-voltage, high-power MOSFETs including Planar, Trench, Super-Junction MOSFETs, and IGBTs, with a focus on design and device characterizations.
• Hands-on skill in designing MOSFET/diode layouts.
• Excellent communication skills to effectively engage with customers, address their needs, resolve issues, and meet demands.

As part of IME Integrated Circuit Design and System Department, we are seeking a candidate with relevant experience in analog integrated circuit design. This candidate will contribute to developing analog circuit blocks e.g. low-power operational amplifiers, voltage/current references, and voltage regulators based on thorough topology analysis. This candidate will work closely with other team members for the circuit design, test verification, as well as system integration and validation for a broad range of innovative sensor systems.

Role & Responsibilities

• Circuit schematic design and simulation, layout supervision, pre-tapeout design verification, test plan development and chip measurement
• Work together with teams to investigate novel circuit/system solutions to create new inventions

Requirements

• Bachelor’s / Master’s degree in Electronic Engineering
• Good understanding of CMOS analog IC design methodologies
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Able to generate high-quality scientific publications and patents
• Team player, quick learner and self-driven

ROLE:
IME is leading the effort to establish the industry leading Silicon Carbide R&D program. This program aims to advance 200mm Silicon Carbide technologies in various areas, such as epitaxy, device design, process integration & fabrication, and power module packaging. The main objective is to drive disruptive innovations in power device research, with a specific focus on >1.2KV power MOSFETs. These innovations are intended to enhance automotive technologies, vehicle electrification, safety measures, sustainable energy grids, and industrial automation. Key aspects to demonstrate for this role include high power device design, novel device concepts, doping design, gate oxidation, and wide-bandgap process simulations. To achieve this, we are seeking individual with extensive industry experience in using Synopsys/Silvaco TCAD simulator, relevant device characterization skills, design simulation development abilities, a willingness to mentor junior staffs, and strong interpersonal skills. The candidate will contribute to the wide-bandgap & Silicon Carbide team by utilizing their device knowledge, guiding team on device characterization, implementing state-of-art Silicon Carbide power MOSFETs (Planar, Trench & Super-Junction), and innovative novel power MOSFETs for future applications.

RESPONSIBILITIES:

• TCAD modeling & simulation, novel high power device design, simulation, and device characterization

• Design and simulate high voltage Silicon Carbide MOSFETs (planar, trench, SJ MOSFET, IGBT) with a blocking voltage of >1.2K using Synopsys/Silvaco simulator

• Design & simulate practical and effective junction terminations

• Provide guidances on device structure, optimizing cell, power/performance analysis, process risk assessment, and recommendations for experimental split and improvement

• Develop and apply fundamental MOS device physics-based TCAD modelling & electric field management to calculate band structure, carrier transport, blocking voltage,
switching properties, and thermal management for vertical power devices in the presence of interface state density, gate oxide defects, and defects in Silicon Carbide

• Model transport and carrier scattering in devices operating in extreme ambient conditions

• Collaborate with diverse teams, including process integration, characterization, and circuit design engineers, to analyze and troubleshoot device-related issues during
development

• Serve as a resource for colleagues with less experience, and lead small projects with manageable risks and resource requirements

• Work closely with both internal and external customers to understand customer issues and align their demands. And grow this wide-bandgap team to ~5 headcounts in the
next 3 years.

JOB REQUIREMENTS:

• PhD in Electrical Engineering or related field

• >10 years industrial experience for high power device design and modeling

• Deep knowledge of high voltage, high power MOSFETs (including Planar, Trench, S-J MOSFETs, and IGBTs) design and device characterization on 4H-SiC & GaN substrates.

• Solid understanding of wide-bandgap semiconductor materials and the strong physics of MOSFET devices

• Ability to teach and transfer knowledge to junior staff members

• Ability to effectively communicate and plan with customers regarding their needs, issues, and demands

ROLE:
IME is leading the effort to establish the industry leading Silicon Carbide R&D program. This program aims to advance 200mm Silicon Carbide technologies in various areas, such as epitaxy, device design, process integration & fabrication, and power module packaging. The main objective is to drive disruptive innovations in power device research, with a specific focus on >1.2KV power MOSFETs. These innovations are intended to enhance automotive technologies, vehicle electrification, safety measures, sustainable energy grids, and industrial automation. Key aspects to demonstrate for this role include high power device design, novel device concepts, doping design, gate oxidation, and wide-bandgap process simulations. To achieve this, we are seeking individual with extensive industry experience in using Synopsys/Silvaco TCAD simulator, relevant device characterization skills, design simulation development abilities, a willingness to mentor junior staffs, and strong interpersonal skills. The candidate will contribute to the wide-bandgap & Silicon Carbide team by utilizing their device knowledge, guiding team on device characterization, implementing state-of-art Silicon Carbide power MOSFETs (Planar, Trench & Super-Junction), and innovative novel power MOSFETs for future applications.

RESPONSIBILITIES:

• TCAD modeling & simulation, novel high power device design, simulation, and device characterization

• Design and simulate high voltage Silicon Carbide MOSFETs (planar, trench, SJ MOSFET, IGBT) with a blocking voltage of >1.2K using Synopsys/Silvaco simulator

• Design & simulate practical and effective junction terminations

• Provide guidances on device structure, optimizing cell, power/performance analysis, process risk assessment, and recommendations for experimental split and improvement

• Develop and apply fundamental MOS device physics-based TCAD modelling & electric field management to calculate band structure, carrier transport, blocking voltage,
switching properties, and thermal management for vertical power devices in the presence of interface state density, gate oxide defects, and defects in Silicon Carbide

• Model transport and carrier scattering in devices operating in extreme ambient conditions

• Collaborate with diverse teams, including process integration, characterization, and circuit design engineers, to analyze and troubleshoot device-related issues during
development

• Serve as a resource for colleagues with less experience, and lead small projects with manageable risks and resource requirements

• Work closely with both internal and external customers to understand customer issues and align their demands. And grow this wide-bandgap team to ~5 headcounts in the
next 3 years.

JOB REQUIREMENTS:

• PhD in Electrical Engineering or related field

• >10 years industrial experience for high power device design and modeling

• Deep knowledge of high voltage, high power MOSFETs (including Planar, Trench, S-J MOSFETs, and IGBTs) design and device characterization on 4H-SiC & GaN substrates.

• Solid understanding of wide-bandgap semiconductor materials and the strong physics of MOSFET devices

• Ability to teach and transfer knowledge to junior staff members

• Ability to effectively communicate and plan with customers regarding their needs, issues, and demands

About NSING:

As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products includes General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low Energy BLE and BMS (Battery Management System). When you join NSING, you will be part of a talented team in the Singapore R&D Center where we develop high performance MCU targeting for Industrial and Edge AI applications.

Your Role:

As a SoC Design Verification Engineer, you will be you would be part of a passionate team developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C co-simulation, to mixed-signal simulation and formal verification. You will be part of the Singapore team in developing high performance MCU chips.

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain test benches for complex digital designs using System Verilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Your Skills and Experiences:

• Education：Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 5 years+ prior industry experience of design verification including significant System Verilog and UVM usage.
• Technical skills:

-Deep knowledge of digital logic design, SOC architecture and microarchitecture

- Proficient in simulation-based verification methodologies and languages such as UVM and System Verilog

- Skilled in developing and maintaining test benches, test cases, and verification environments

- Experience across the full verification cycle from initial planning to final tape out

• Preferred skills:

- Knowledge of low-power design techniques and verification methodologies.

- Knowledge of hardware-software co-simulation mixed-signal verification techniques.

- Knowledge of gate level simulation methodologies.

Other Skills:

• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Flexibility and adaptability and demonstrates ability to manage multiple tasks and projects, prioritizing effectively to meet deadlines.

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.
  

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. 2 years of relevant experience in similar field.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

The Bioinformatics Institute (BII), Agency for Science, Technology and Research (A*STR) is seeking applications for an outstanding scientist in the field of quantum computing.

The Bioinformatics Institute (BII) is a computational biology research and postgraduate training institute as well as a national resource centre in bioinformatics within the Biomedical Research Council (BMRC) of A*STAR. Our scientists aim to understand the biomolecular mechanisms that underlie biomedical phenomena by developing sophisticated computational methods to support discovery from a secure and sustainable data hub to cross-disciplinary AI/ML analysis and data integration. We analyse a wide spectrum of biological and clinical data, including omics data (biomolecular sequences, expression profiles, epigenetics data), 3D structures of macromolecules, and biological tissue and macroscopic images from local and international academic, hospital and industry collaborators, public resources and also from in-house efforts. The institute has a vibrant and diverse research portfolio that includes infectious diseases, computational toxicology, precision medicine, oncology and drug discovery.

Job scope and responsibilities:

· Lead efforts in using quantum computing to analyze biomolecular and biomedical data (e.g. protein-ligand interactions, molecular docking, protein/RNA folding, molecular dynamics simulations, imaging, spatial ohmics) and couple it with methods such as quantum machine learning, quantum monte carlo etc, contributing to the development of a broader initiative encompassing AI in drug discovery.

· Collaborate closely with scientists within the Bioinformatics Institute, within A*STAR and within the local ecosystem.

· Lead or participate in research grant proposals.

Requirements:

· Minimum PhD in a related field.

· 5 years or more of postdoctoral experience in quantum computing, demonstrating outstanding research outcomes and strong publication records.

· The candidate must have experience in quantum computing software development/applications, especially with NISQ machines.

· Excellent communication (oral and written) and public speaking skills.

· Strong records of strategic thinking ability.

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.

Main Duties & Responsibilities

• Develop key relationships (Marketing and Operations) by providing design solutions that met needs and budgets without compromising quality or design intent.
• Manage contractors and the design process to ensure design excellence and quality, and that deliverables meet company standards and project briefs.
• Resolve interior design issues and any other technical issues related to interior design in a timely manner.
• Conduct brainstorming sessions, maintaining strategic and creative thinking to develop innovative and actionable creative initiatives in a fiscally responsible manner.
• Conduct site visits as necessary to ensure implementation and compliance of key interior design items with approved design intent and direction.
• Monitoring and reporting to senior management on the progress of interior design work on projects.
• Constantly stay updated on the latest interior design trends to enhance ideas for design concepts and overall drawing perspectives.
• Implementing an appropriate and effective project or programme management framework for corporate interior fit-out projects.
• Conduct feasibility studies, project planning, tendering, contract, and project administration.
• Liaising and obtaining authorities' approval at various stages of work.

Job Requirements

• Min Diploma in interior design/facility management/project management.
• Minimum 3 years of relevant experience.
• Preferably with work experience in designing in the F&B industry or regional capacity.
• Excellent communication and presentation skills, both written and verbal.
• Proficiency in design software (e.g., AutoCAD, Revit, SketchUp).
• A passion for design and a commitment to delivering exceptional results.
• Experience in managing contractors, vendors, partners, and internal teams such as operations and marketing.

What you will do

• APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process
• Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process
• Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECO

What you bring

• Apr hands on for n5/n4/n3e process using Innovus and Fusion compiler EDA tool
• tcl/csh/perl/bash. programming skill
• Timing Analysis Debugging and Fixing skills
• Experienced N4/N3e process

Job Description:

- Perform Civil, Structural Analysis and Design to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- To Lead and Mentor Junior Engineer in Performing Engineering Task

- Reporting to Principal Engineer / Management

Job Requirements:

- Candidate must possess at least a Master's Degree /Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 4 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

Responsibilities:

• Lead the design and development of a vision module for equipment used in the semiconductor industry
• Collaborate with cross-functional teams to define project requirements and specifications
• Design and test electronic circuits, components, and systems for optimal performance and reliability
• Develop hardware prototypes and perform validation testing to ensure functionality and compliance with industry standards
• Work closely with software engineers to integrate the vision module with existing systems and interfaces
• Provide technical support and guidance to junior engineers and team members
• Stay current on industry trends and advancements in technology to ensure our products remain competitive and innovative

Qualifications:

• Bachelor's degree in Electrical Engineering or related field; Master's degree preferred
• 5+ years of experience in electrical, electronic, and hardware design for industrial applications
• Proficiency in hardware design and experienced with vision systems, image processing, and camera technology is highly desirable
• Familiarity with industry standards and regulations for semiconductor equipment
• Excellent communication skills and ability to work collaboratively in a team environment
• Strong problem-solving skills and attention to detail
• Able to communicate effectively in both English and Chinese with our local and China based teams

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 3 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Candidates with no prior working experience are welcome to apply.

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-Level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 5 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

About NSING:

As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products includes General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low Energy BLE and BMS (Battery Management System). When you join NSING, you will be part of a talented team in the Singapore R&D Center where we develop high performance MCU targeting for Industrial and Edge AI applications.

Your Role:

As a SoC Design Verification Engineer, you will be you would be part of a passionate team developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C co-simulation, to mixed-signal simulation and formal verification. You will be part of the Singapore team in developing high performance MCU chips.

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain test benches for complex digital designs using System Verilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Your Skills and Experiences:

• Education：Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 5 years+ prior industry experience of design verification including significant System Verilog and UVM usage.
• Technical skills:

-Deep knowledge of digital logic design, SOC architecture and microarchitecture

- Proficient in simulation-based verification methodologies and languages such as UVM and System Verilog

- Skilled in developing and maintaining test benches, test cases, and verification environments

- Experience across the full verification cycle from initial planning to final tape out

• Preferred skills:

- Knowledge of low-power design techniques and verification methodologies.

- Knowledge of hardware-software co-simulation mixed-signal verification techniques.

- Knowledge of gate level simulation methodologies.

Other Skills:

• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Flexibility and adaptability and demonstrates ability to manage multiple tasks and projects, prioritizing effectively to meet deadlines.

Job Description:

As a Project Executive in Interior Design, you will be responsible for overseeing the planning, coordination, and execution of design projects. You will manage a team of designers, liaise with clients, and ensure that all projects are delivered on time, within budget, and to the highest standards of quality.

Key Responsibilities:

• Lead and manage multiple interior design projects simultaneously, from initial concept to final installation.
• Develop project timelines, budgets, and resource allocations.
• Collaborate with clients to understand their vision and requirements, providing expert guidance throughout the design process.
• Coordinate with architects, contractors, and vendors to ensure design integrity and successful execution.
• Monitor project progress, conduct site visits, and implement corrective actions as necessary.
• Facilitate communication between internal teams and external stakeholders to ensure alignment and transparency.
• Prepare and present project updates and reports to clients and senior management.

About Us

Our Febreze, Home Care organization is looking for an experienced product design candidate to join our Air Care Membrane platform team, curious to lead the technology development and define Febreze's new S-curve. This is an exciting role for a Product Design Senior Scientist who is passionate about growing the Air Care business.

In this role, you will be a critical team player and partner for Global Febreze team to lead the product design and development of Membrane (Continuous Non Energized) Platform to enable Febreze's vision to cross $2Billion. Together we will define the Febreze's Innovation Master Plan across all consumer jobs to be done.

Your team

Located at the P&G Singapore Innovation Center, you will be part of Air Care Product Design team in Fabric and Home care sector. You will have the opportunity to work with multi-functional teams and engage with both internal and external partners.

Key Responsibilities

• Responsible for introducing fundamentally new technologies, formulations, materials & processes, developing complex technical solutions for meeting consumer propositions.
• Responsible for Technical Project Management, IP strategy, leading Technical readiness assessment, co-creating and influencing the strategic direction of the research work to be done
• Prtnering with other P&G Innovation centers to bring new ideas to life and make a global impact.
• Coaching Researchers and Lab technician of the group in development and delivery of innovation

Qualifications

• Masters degree in Science or Engineering
• 8+ years experience in Product Design/Development and Formulation in FMCG industry
• Able to Lead global programs with excellent cross functional collaboration and project management skills
• Strong technical mastery and a high level of technical and consumer curiosity.
• Ability to build a strong relationship and network both with the R&D and the multifunctional teams.
• Ability to drive analysis and conclusions of technical and consumer work both via written and oral communication.
• High agility and ability to Embrace Change, as midstream work can be both uncertain and shift in priority according to new learning and overall business priorities.
• Leadership and a Passion for Winning by driving projects to success. The candidate should be comfortable with a degree of ownership and independence to lead by example, executing with excellence and using influencing skills to engage both the R&D and the multifunctional team

About us

We produce globally recognized brands and we grow the best business leaders in the industry. With a portfolio of trusted brands as diverse as ours, it is paramount our leaders are able to lead with courage the vast array of brands, categories and functions. We serve consumers around the world with one of the strongest portfolios of trusted, quality, leadership brands, including Always®, Ariel®, Gillette®, Head & Shoulders®, Herbal Essences®, Oral-B®, Pampers®, Pantene®, Tampax® and more. Our community includes operations in approximately 70 countries worldwide.

Visit http://www.pg.com to know more.

Our consumers are diverse and our talents - internally - mirror this diversity to best serve it. That is why we’re committed to building a winning culture based on Inclusion and our ideal candidate is passionate about the same principle: you will join our daily effort of being “in touch” so we craft brands and products to improve the lives of the world’s consumers now and in the future. We want you to inspire us with your unrivaled ideas.

We are committed to providing equal opportunities in employment. We do not discriminate against individuals on the basis of race, color, gender, age, national origin, religion, sexual orientation, gender identity or expression, marital status, citizenship, disability, veteran status, HIV/AIDS status, or any other legally protected factor.

Job Description:

- Perform Civil, Structural Analysis and Design to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- To Lead and Mentor Junior Engineer in Performing Engineering Task

- Reporting to Principal Engineer / Management

Job Requirements:

- Candidate must possess at least a Master's Degree /Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 4 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage