Job Responsibilities:
· Manage a team of analog layout engineers, providing leadership, mentorship, and technical guidance.
· Oversee the layout design, and verification in technologies such as CMOS etc.
· Collaborate with design and PD teams to translate circuit designs into physical layouts.
· Ensure the team meets project schedules and deliverables, maintaining the highest quality standards.
· Conduct layout reviews to ensure design compliance with specifications and adherence to industry best practices.
· Coordinate with cross-functional teams for debugging, yield improvement, and issue resolution.
· Contribute to layout process and methodology improvements and automation.
· Stay updated with the latest technology trends and advancements in the field of analog layout design.
Requirements:
· Bachelor’s or Master’s degree in Electrical Engineering or related field.
· Minimum of 7 years of experience in analog layout design with at least 2 years in a management or team lead role.
· Proficiency in industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler and Mentor Graphic Calibre.
· Deep understanding of semiconductor physics, device fabrication processes, and layout techniques.
· Experience in managing layout designs for a variety of analog circuits, including power, high speed, mixed signal, etc.
· Exceptional leadership skills with a proven ability to manage and develop a high-performing team.
· Strong analytical skills with the ability to solve complex technical problems.
· Excellent communication skills with the ability to clearly articulate technical concepts.
· Experience with advanced FinFET process nodes e.g., TSMC 5/6nm.