Hardware Architect (AI Sub-system)
Overview
We are seeking a talented and motivated Hardware Architect (AI Sub-system) to join our R&D team to own, define, and drive exploration and design of the next generation hardware for AI sub-system in high performance computing (HPC) SoCs.
Our division’s mission is to use the latest AI and cloud technologies to develop the best AI inference for advanced driver safety engineers building self-driving vehicles and other high performance compute products. Renesas is the leading automotive electronics supplier globally, and this is a rare opportunity to develop the infrastructure required to deploy our AI software to the billions of devices we ship to customers every year. You will join our newly formed AI & Cloud Engineering organization of around 100 software engineers. Due to strong demand for our AI-related products we are planning to triple in size in the next three years, so there is lots of room for you to help us grow the team together while remaining small. Our team’s key locations are Tokyo, London, Paris, Dusseldorf, Beijing, Singapore, Ho Chi Minh City, and other metropolitan areas, but you can also join fully remotely from other locations globally or get our support to relocate to our key hubs such as Tokyo.
Responsibilities
- Participate and lead in the architecture design of next generation multi-core AI sub-system including CPU/DSP/NPU, memory hierarchies, scalable interconnects, etc.
- Perform HW/SoC architectural modeling, performance analysis, trade-off analysis, PPA optimization, etc.
- Deliver architecture specifications to design teams and articulate them effectively across stakeholders ranging from system and software teams to architecture peers, and to technology leadership.
- Collaborate with silicon and platform bring-up to verify and debug the AI sub-system and its delivered performance.
Qualifications
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or related field; Ph.D. is a plus.
- 10 years of experience in SoC and/or ASIC architecture and design.
- Prior direct experience (> 5 years) in NPU architecture design.
- Good knowledge of architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation.
- Good knowledge of AMBA bus infrastructure (ACE/AXI/AHB).
- Good knowledge of memory subsystems and memory hierarchy designs, including cache coherence protocols, memory models, and NUMA architectures.
- Good coding skill in C/C++ and Verilog/System Verilog.
- Working knowledge of ARM and/or RISCV CPU.
- Working knowledge of existing simulation capabilities (GEM5, FastSIM, Platform Architect) or create new simulation capabilities when necessary
- Good understanding of current and emerging compute architectures for HPC workload is a plus.
- Experience in NPU, GPU, and micro-processor development is a plus; especially multi-core systems.
- Knowledge of CXL is a plus.
- Knowledge and expertise in ARM and/or RISCV ISAs is a plus.
- Knowledge of Python is a plus.
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EA Reg. ID: R22109658 (Teng Yong Yao)
EA License No.: 01C4394
