As a Principal Engineer/MTS at Micron Technology, Inc., you will be part of the team driving effort to accelerate NAND development learning cycles to achieve best in class cycle time from first silicon to qualified system. You will be part of a forward-thinking team of engineers that solves complex problems, responsible for enabling Micron’s products with flawless and issue free release to both internal and external customers.
You will be engaged in developing, validating, characterizing, and qualifying Micron’s next generation 3D NAND memory products to power our customers’ innovation. The future of non-volatile memory and the systems that utilize the advanced technology will continue to be exciting and dynamic. Micron is seeking experienced individuals that find technical challenges engaging and invigorating.
Key Responsibilities :
- Innovate new DFT solutions to reduce the DPM, Test time, yield hit, cycle time for qualification
- Partner with Design Engineering team in Testmode development and innovations
- Own Testmodes Definition to ensure all testing requirements are fulfilled
- Drive testmode validation process in pre-silicon and post-silicon phase in collaboration with other PE teams
- First responders to Silicon DFT related issues, driving silicon debug and experiments to come up with the most practical solution
- Enable best-in-class production testing capabilities and test time efficiencies for cost reductions
- Lead efforts from PE side to reduce the die size
- Enable faster development of production DIDs by providing learnings from the spider chips
- Engage with System teams on innovation and solutions for defect management, improving yield and cycle time for qualification
- Lead staging and strategy on future nodes to achieve best in class Design and System solutions to improve yield, quality, and test time
- Employ analytical skills for high volume data analysis
- Guide , mentor, support all the reports with technical expertise, providing them direction for enablement of solutions
Requirements
- Degree (Bachelor’s, Master’s, or PhD) in Electrical and Electronics Engineering with 15+ years of experience
- Strong knowledge of CMOS technology and NAND/DRAM development
- Proficient in tackling challenges, leveraging extensive experience in design rule, process and product qualifications in logic or memory (NAND/DRAM/SRAM) (a strong plus)
- Proficient in ASIC design flow: RTL design, verification, logic synthesis, and timing analysis.
- Familiar with DFT flow and verification
- Experience with digital and analog simulation tools (e.g., Finesim, Hspice, Hsim, Verilog)
- Experience with System Verilog testbench/UVM/Constrained Random verification (a plus)
- Skilled in RTL development for logic or mixed-signal circuits
- Experience in leading and mentoring engineering teams would be a strong plus
