Total 18 staff nurse job vacancies in Art / Design / Entertainment category in d12 balestier serangoon toa payoh

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Fast hiring process, start 2nd December 2024!
Short term - 2mths commitment (extendable and can convert to perm)

Benefits:

• Basic Salary up to $4,400 with yearly increment based on performance.
• 5.5 days work week (Monday to Friday, 9am - 6pm / Saturday, 9am – 1pm)

Job Description:

This is a full time role for an Enrolled Nurse located in Novena. Our client provided health and wellness service.The role involves supporting nursing and clinical duties, including tasks like phlebotomy, vaccinations, and wound care, while assisting doctors during minor procedures. Responsibilities also cover managing medications, maintaining inventory, handling medical records, and providing both clinical and administrative support to ensure smooth clinic operations. Additionally, the job includes scheduling patient appointments, booking referrals, and managing patient inquiries. You'll also assist surgeons during procedures and carry out any other duties as directed by management.

Qualifications:

• Nitec or Diploma in Nursing and above
• At least 2 years of working experience in clinic setting
• Registered with Singapore Nursing Board
• Preferred Nurses have experience in assisting doctor with procedure

Job Responsibilities:-

• Utilize in-depth knowledge of Foundation IP to evaluate and qualify IP’s. Able to benchmark and optimize Std cells/IO’s/memory for optimum performance, area or power needs of a project
• Conduct Spice simulations to verify the performance and reliability of designs on RC extracted netlists
• Perform library characterization to ensure accurate timing, power, and area models. Stay up-to-date with industry trends and emerging technologies in library characterization and PPA analysis
• Help to develop and maintain EDA automation scripts to streamline CAD flow and design processes
• Modify and optimize IPQA scripts to improve efficiency and performance
• Analyze and understand both hard and soft IPs within SOC designs. Work with IP vendors to deliver custom specs needed for MXL project needs
• Review silicon reports and provide detailed analysis to identify and resolve issues
• Work closely with vendors and cross-functional teams to ensure successful project outcomes. Collaborate with design teams to ensure seamless integration of libraries and IP blocks
• Maintain comprehensive documentation of IP Vendor engagement. Troubleshoot and resolve issues related to IP, EDA tools and automation flows

Job Requirements:-

• Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or a related field
• Minimum 10 years of experience in design engineering or a related field. Good understanding of the IC design flow, including front-end and back-end processes
• Proficiency in Foundation IP, Spice Simulation, Library Characterization, EDA automation scripts, and IP script modifications. Familiarity with library characterization tools such as Liberate, Cadence Genus, or Synopsys Library Compiler
• Strong ability to review and analyze silicon reports and provide detailed insights. Excellent analytical and problem-solving skills
• Excellent interpersonal and communication skills for effective collaboration with vendors and team members
• Experience with advanced node technologies (e.g., 8nm, 4nm, and below)
• Experience with SOC IP design and verification
• Knowledge of emerging technologies such as FinFET, FD-SOI, or III-V semiconductors
• Familiarity with industry-standard EDA tools and methodologies
• Experience with tools such as Synopsys PrimeTime, Cadence Genus, or Mentor Graphics Questa

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Job Responsibilities:-

• Responsible for pre-silicon RTL coding of block, subsystem and top level SOC Integration
• Develop robust and reusable Code and ensure VHDL or Verilog implementation enables readiness for Verification, Synthesis, DfT and Low Power Insertion
• Develop reusable RTL Code, using Generic and Modular Coding Styl
• Contribute to verification plan from specification and in coordination with architects
• Collaborate on Timing constraints, Testability and Insertion of Low Power Structure such as Power gating, Isolation and Retention Sequential Elements
• Own Linting, CDC, RDC and collaborate with Verification Team and Physical Design
• Co-work with Architecture/ Design/Validation/SW teams. Own cross functional micro-architecture and implementation and drive issues to closure

Job Requirements:-

• Bachelor Degree or Master's in Electronics Engineering with 8 to 10 years and above of related working experience
• Expert in VHDL and Verilog Coding, Front End Design using best-in-class methodology and Micro-architecture
• Good experience in developing Multi-Million gates IP and integrated heterogenous complex SoC, including Analog and Mixed Signal IP
• Participated in Micro-architecture Specification
• Familiar with Hardware-Software Partitioning, Multi-CPU and Multi-Core Architecture
• Deep knowledge and understanding of NoC and multi-layer complex Interconnect Systems
• Solid verification skills in problem solving, constrained random testing and debugging
• Deep understanding of design architecture and possess meticulous attention to details
• Expertise with Code Linting tools and Static Code checker such as Spyglass, Real Intent, etc
• Expertise in IP-XACT, Connectivity Checks, Register Interfaces and RTL Assembly Tools
• Programming experience in C/C++/assembly/SVA
• Good experience in working with ARM and ARM Eco-system, AXI, AHB, SERDES systems, communication peripherals(UART, I2C, SPI) and power management
• Experience in WiFi/DOCSIS/Ethernet/DSP/DDR is a plus
• Setup Automated regressions environment and in general automate repetitive verification tasks to enhance productivity
• Strong team player and communicator

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Job Responsibilities:-

• Collaborate with concept team on frontloading activities to develop and review high level specification
• Develop micro-architecture of digital blocks/modules
• RTL design using VHDL/Verilog HDL coding
• Perform quality checks e.g. Linting, CDC, code coverage
• Collaborate with functional verification team on test plan and debug/fix failing test cases
• Provide synthesis constraints and involve in DFT insertion, timing closure and area optimizations
• Pre/post-silicon system validation debug and bring up support
• Prepare micro-architecture document for detailed design reviews with project team
• Prepare task list, effort estimate and commit to schedule

Job Requirements:-

• Degree or Master's in Electronics and Communication Engineering or equivalent with focus on Digital Design
• Minimum 8 years of ASIC or SoC/IP design experience
• Hands-on experience in micro architecture development, RTL coding, linting, CDC, constraining timing paths
• Basic understanding on verification and test cases development
• Pre/post-silicon system validation debug and bring up support
• Familiarity with Synopsys and Cadence EDA tools for simulation and quality checks
• Know-how of low power techniques and methodology
• System knowledge in communication domain and its interface protocols
• Knowledge of packet processing, Ethernet interface protocols and standard , clock and reset and CPU subsystem
• Strong ability to use analytical skills to solve complex problems
• Good communication and interpersonal skills
• Experience to work with cross functional and multi-site teams

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Job Responsibilities:-

• Responsible for toplevel and blocks whose complexity is at the limit of current tool capacity
• Responsible for all aspects of physical implementation, include floor-planning, physical synthesis, clock-tree synthesis, parasitic extraction
• Responsible for IO ring design and bump implementation, meeting ESD, EMI and SSO requirements
• Implementation of Low power layout methodology (multiple switchable power domains, level shifter)
• Execution of static and dynamic drop, ramp up analysis using Redhawk
• Perform static timing analysis to handle complex timing closure
• Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues

Job Requirements:-

• Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design with minimum 5 years or more related experience
• Experience with complex Low Power SOC in 16nm/7nm, 5nm is a plus
• Good experience with Cadence or Synopsys implementation tool (Tempus, Innovus, DC, ICC2, Fusion Compiler), experience with Cadence implementation tool is a plus
• Experience in Mentor Verification tool, Calibre
• Experience in Redhawk
• Proficient in TCL code, python knowledge is a plus
• Able to work in a multi-cultural team with a strong drive to excel
• Good written and communication skills

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

Meet the Team

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

Responsibilities

The chosen candidate will contribute to, and manage a team for, the development of architecture, microarchitecture, and design of complex, low power, Wireless SoCs. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML, while meeting best-in-class power and performance targets. The Chip Design lead will define architectures with embedded multi-core, multi-threaded processor subsystems, AI accelerators, bus interconnect, memory architecture and multi-level caches to satisfy performance and throughput requirements. This will include RISC-V, ARM or proprietary processor designs, high-speed interfaces for off-chip memories, integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process.

• Lead the development and execution of Wireless SoC’s from definition, through execution, and into production
• Definition and Planning
  Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates.
  Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse.
  Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies.
• Project Execution
  Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation.
  Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure.
  Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams.
  Follow established quality procedures and processes to achieve first tapeout.
• Validation to Production
  Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification.
  Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary

Skills You Will Need

Minimum Qualifications:

• B.Tech/M.Tech in related branches of electronics and computer science with a minimum of 10 years of related experience.
• Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus.
• Top-down planning and execution of SOC projects.
• Experience in full-chip development cycle
• Able to build strong technical team.
• Hands-on experience in architecture, micro-architecture, digital design processes
• Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
• Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
• Knowledge of processors like RISC-V and ARM processors
• Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
• Knowledge of DFT including Scan, ATPG, MBIST
• Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
• Knowledge of hardware accelerators
• Knowledge of Verilog and System Verilog
• Knowledge of scripting languages like Perl, Python, Tcl, shell

Benefits & Perks:

You can look forward to the following benefits:

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station

About the Team

The Digital Subsystems team is responsible for the research and development of digital architectures and IPs from concept to production. We develop compute engines (AI/ML), processors (RISC-V), accelerators, peripherals and system IP. Our activities include advanced research & development, high-level modeling, architecture, RTL design, timing/power/area optimization, formal and UVM verification within an automated framework. We value innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team.

What we’re looking for:
The Verification Lead will be responsible for technical leadership, direction-setting and significant hands-on contribution of advanced digital verification projects. The lead will have direct responsibility for the planning and execution of methodology and flows to be employed in the execution of verification projects. The lead will directly supervise the technical activities of verification projects such as test planning, execution, and reviews at both IP and system-levels. Included is communicating and synchronizing methodology and test development with verification leads and engineers at other sites. The lead is also expected to provide technical coaching and mentoring to team members on verification approaches, languages, and tools/methodologies.

Skills you’ll need:

• Provide technical leadership for a team of verification engineers
• Generate and execute verification plan based on specifications
• Architect and implement testbenches using UVM-based constrained-random
• Utilize architectural models to verify functionality of digital IP
• Develop integration and reuse guidelines for IP integration
• Coverage definition, implementation, and analysis
• Mentor junior engineers
• Support IC teams in integration and use of IPs
• Develop and improve flows and methodologies for efficient and high-quality development
• Skill development and training on modern verification techniques such as formal

Required Experience & Skills:

• Technical Team leadership and project execution ownership
  Ability to plan, track and manage a complex verification project comprising of a team of engineers
  Ability to mitigate unforeseen obstacles and maintain on-time execution to meet project schedules
  Technical leadership and mentorship
• Extensive experience with implementation of UVM testbenches:
  Verification component design with emphasis on decoupled stimulus and checking, robust random stimulus generation and reuse
  Reuse of IP-level testbenches in subsystem and system-level verification
  Assertion-based verification
• Ability to define and specify requirements for verification-related flows including:
  Simulation control and coverage
  Regression deployment and coverage collection
• Experience with EDA simulation tools

Preferred Experience & Skills (any of the below):

• Experience in deploying and maintaining formal verification applications for system-level connectivity verification.
• Experience in deploying and maintain formal property verification at an IP-level for interface protocol and internal functional verification.
• Experience in developing and deploying executable and reusable test plans and tracking their closure through regression
• Experience in verification of microprocessors
  Developing and debugging assertions with formal property verification for interface verification and/or internal processor operation
  Experience with processor debug techniques and design including test interfaces, debug and trace implementation and general debug infrastructure
  Experience developing and maintaining software toolchain and infrastructure to facilitate software testing of processor implementations.

​

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station

Job description:

• Assisting with the preparation of ingredients, measuring and mixing ingredients according to recipes, and cutting, slicing, and dicing ingredients for dishes.
• Responsible for cooking dishes, grilling meats, sautéing vegetables, and other cooking tasks as assigned by the head chef or supervisor.
• Assisting with cleaning kitchen equipment, dishes, and utensils, sweeping and mopping floors, and wiping down surfaces to maintain a clean and hygienic environment.
• Responsible for restocking supplies such as food, drinks, and condiments, and monitoring inventory levels to ensure that the kitchen is always fully stocked.
• Ensuring that they are stored properly. Maintaining a clean and safe kitchen environment.

Requirements

• At least 1 year relevant working experience
• Cheerful pleasant personality with a positive mindset
• Bilingual or multilingual ability is an added plus
• Possess Hygiene Certification as an added bonus
• Ability to carry out required tasks in an accurate manner
• Possess skills in the proper handling of kitchen equipment
• Available on short notice

Added Information

• Full-time – up to S$2000, 44 Hours/week; 5.5 Workdays
• Part-time – between S$10 - S$12 per hour, rotating shifts (Based on experience)

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least five years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered.

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

Job Responsibilities:-

• Responsible for toplevel and blocks whose complexity is at the limit of current tool capacity
• Responsible for all aspects of physical implementation, include floor-planning, physical synthesis, clock-tree synthesis, parasitic extraction
• Responsible for IO ring design and bump implementation, meeting ESD, EMI and SSO requirements
• Implementation of Low power layout methodology (multiple switchable power domains, level shifter)
• Execution of static and dynamic drop, ramp up analysis using Redhawk
• Perform static timing analysis to handle complex timing closure
• Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues

Job Requirements:-

• Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design with minimum 5 years or more related experience
• Experience with complex Low Power SOC in 16nm/7nm, 5nm is a plus
• Good experience with Cadence or Synopsys implementation tool (Tempus, Innovus, DC, ICC2, Fusion Compiler), experience with Cadence implementation tool is a plus
• Experience in Mentor Verification tool, Calibre
• Experience in Redhawk
• Proficient in TCL code, python knowledge is a plus
• Able to work in a multi-cultural team with a strong drive to excel
• Good written and communication skills

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability

We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.

Meet the Team

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

As Senior Staff Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips.

Responsibilities

• Block and IP Verification
• Block-level verification to validate block performance and adherence to requirements
• Generate and execute verification plan based on specifications
• Architect and implement test benches using UVM-based constrained-random and formal methods
• Coverage definition, implementation, and analysis
• Formal Verification of mixed-signal IP integration, including real-number modeling
• SoC Integration and Verification
• Define, test and debug use cases for the SoC
• Verify and debug low-power design
• Flows and Methodology
• Improve flows and methodologies to streamline IP development and integration.

Skills You Will Need
Minimum Qualifications:

• Min. 15 years of IC design experience for senior positions. Open to junior candidates with strong foundation.
• Industry experience developing test benches and verification components with SystemVerilog and UVM is required
• Knowledge of scripting/language (Python, PERL, shell, TCL)
• Design/Verification skills such as Software/Firmware coding (C), SystemVerilog Assertion and coverage analysis, Low-power implementation (UPF), Mixed Signal Real Number Modeling (RNM, Spice)

Benefits & Perks:
You can look forward to the following benefits:

• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• Flexible work policy